/* Generated automatically by the program `gencodes' from the machine description file `md'. */ #ifndef GCC_INSN_CODES_H #define GCC_INSN_CODES_H enum insn_code { CODE_FOR_nothing = 0, CODE_FOR_x86_fnstsw_1 = 47, CODE_FOR_x86_sahf_1 = 48, CODE_FOR_kmovw = 91, CODE_FOR_movsi_insv_1 = 118, CODE_FOR_movdi_insv_1 = 119, CODE_FOR_swapxf = 130, CODE_FOR_zero_extendqidi2 = 134, CODE_FOR_zero_extendhidi2 = 135, CODE_FOR_zero_extendqisi2_and = 136, CODE_FOR_zero_extendhisi2_and = 137, CODE_FOR_zero_extendqihi2_and = 140, CODE_FOR_extendsidi2_1 = 143, CODE_FOR_extendqidi2 = 144, CODE_FOR_extendhidi2 = 145, CODE_FOR_extendhisi2 = 146, CODE_FOR_extendqisi2 = 148, CODE_FOR_extendqihi2 = 150, CODE_FOR_truncxfsf2_i387_noop = 164, CODE_FOR_truncxfdf2_i387_noop = 165, CODE_FOR_fix_truncsfsi_sse = 170, CODE_FOR_fix_truncsfdi_sse = 171, CODE_FOR_fix_truncdfsi_sse = 172, CODE_FOR_fix_truncdfdi_sse = 173, CODE_FOR_fix_trunchi_fisttp_i387_1 = 174, CODE_FOR_fix_truncsi_fisttp_i387_1 = 175, CODE_FOR_fix_truncdi_fisttp_i387_1 = 176, CODE_FOR_fix_trunchi_i387_fisttp = 177, CODE_FOR_fix_truncsi_i387_fisttp = 178, CODE_FOR_fix_truncdi_i387_fisttp = 179, CODE_FOR_fix_trunchi_i387_fisttp_with_temp = 180, CODE_FOR_fix_truncsi_i387_fisttp_with_temp = 181, CODE_FOR_fix_truncdi_i387_fisttp_with_temp = 182, CODE_FOR_fix_truncdi_i387 = 186, CODE_FOR_fix_truncdi_i387_with_temp = 187, CODE_FOR_fix_trunchi_i387 = 188, CODE_FOR_fix_truncsi_i387 = 189, CODE_FOR_fix_trunchi_i387_with_temp = 190, CODE_FOR_fix_truncsi_i387_with_temp = 191, CODE_FOR_x86_fnstcw_1 = 192, CODE_FOR_x86_fldcw_1 = 193, CODE_FOR_floathisf2 = 194, CODE_FOR_floathidf2 = 195, CODE_FOR_floathixf2 = 196, CODE_FOR_floatsixf2 = 197, CODE_FOR_floatdixf2 = 198, CODE_FOR_floatdisf2_i387_with_xmm = 207, CODE_FOR_floatdidf2_i387_with_xmm = 208, CODE_FOR_floatdixf2_i387_with_xmm = 209, CODE_FOR_addqi3_cc = 219, CODE_FOR_addsi_1_zext = 222, CODE_FOR_addqi_ext_1 = 244, CODE_FOR_adcxsi3 = 295, CODE_FOR_adcxdi3 = 296, CODE_FOR_divmodsi4_1 = 335, CODE_FOR_divmoddi4_1 = 336, CODE_FOR_divmodhiqi3 = 343, CODE_FOR_udivmodsi4_1 = 344, CODE_FOR_udivmoddi4_1 = 345, CODE_FOR_udivmodhiqi3 = 352, CODE_FOR_kandnqi = 375, CODE_FOR_kandnhi = 376, CODE_FOR_andqi_ext_0 = 384, CODE_FOR_kxnorqi = 410, CODE_FOR_kxnorhi = 411, CODE_FOR_kortestzhi = 412, CODE_FOR_kortestchi = 413, CODE_FOR_kunpckhi = 414, CODE_FOR_copysignsf3_const = 472, CODE_FOR_copysigndf3_const = 473, CODE_FOR_copysigntf3_const = 474, CODE_FOR_copysignsf3_var = 475, CODE_FOR_copysigndf3_var = 476, CODE_FOR_copysigntf3_var = 477, CODE_FOR_x86_64_shld = 490, CODE_FOR_x86_shld = 491, CODE_FOR_x86_64_shrd = 520, CODE_FOR_x86_shrd = 521, CODE_FOR_ashrdi3_cvt = 522, CODE_FOR_ashrsi3_cvt = 523, CODE_FOR_ix86_rotldi3_doubleword = 565, CODE_FOR_ix86_rotlti3_doubleword = 566, CODE_FOR_ix86_rotrdi3_doubleword = 567, CODE_FOR_ix86_rotrti3_doubleword = 568, CODE_FOR_setcc_sf_sse = 594, CODE_FOR_setcc_df_sse = 595, CODE_FOR_jump = 636, CODE_FOR_blockage = 655, CODE_FOR_prologue_use = 657, CODE_FOR_simple_return_internal = 658, CODE_FOR_simple_return_internal_long = 659, CODE_FOR_simple_return_pop_internal = 660, CODE_FOR_simple_return_indirect_internal = 661, CODE_FOR_nop = 662, CODE_FOR_nops = 663, CODE_FOR_pad = 664, CODE_FOR_set_got = 665, CODE_FOR_set_got_labelled = 666, CODE_FOR_set_got_rex64 = 667, CODE_FOR_set_rip_rex64 = 668, CODE_FOR_set_got_offset_rex64 = 669, CODE_FOR_eh_return_internal = 670, CODE_FOR_leave = 671, CODE_FOR_leave_rex64 = 672, CODE_FOR_split_stack_return = 673, CODE_FOR_ffssi2_no_cmove = 674, CODE_FOR_bmi_bextr_si = 695, CODE_FOR_bmi_bextr_di = 696, CODE_FOR_bmi2_pdep_si3 = 707, CODE_FOR_bmi2_pdep_di3 = 708, CODE_FOR_bmi2_pext_si3 = 709, CODE_FOR_bmi2_pext_di3 = 710, CODE_FOR_tbm_bextri_si = 711, CODE_FOR_tbm_bextri_di = 712, CODE_FOR_bsr_rex64 = 731, CODE_FOR_bsr = 732, CODE_FOR_bswaphi_lowpart = 746, CODE_FOR_paritydi2_cmp = 747, CODE_FOR_paritysi2_cmp = 748, #define CODE_FOR_tls_initial_exec_64_sun CODE_FOR_nothing CODE_FOR_truncxfsf2_i387_noop_unspec = 809, CODE_FOR_truncxfdf2_i387_noop_unspec = 810, CODE_FOR_sqrtxf2 = 811, CODE_FOR_sqrt_extendsfxf2_i387 = 812, CODE_FOR_sqrt_extenddfxf2_i387 = 813, CODE_FOR_fpremxf4_i387 = 817, CODE_FOR_fprem1xf4_i387 = 818, CODE_FOR_sincosxf3 = 825, CODE_FOR_sincos_extendsfxf3_i387 = 826, CODE_FOR_sincos_extenddfxf3_i387 = 827, CODE_FOR_fptanxf4_i387 = 828, CODE_FOR_fptan_extendsfxf4_i387 = 829, CODE_FOR_fptan_extenddfxf4_i387 = 830, CODE_FOR_fpatan_extendsfxf3_i387 = 832, CODE_FOR_fpatan_extenddfxf3_i387 = 833, CODE_FOR_fyl2xxf3_i387 = 834, CODE_FOR_fyl2x_extendsfxf3_i387 = 835, CODE_FOR_fyl2x_extenddfxf3_i387 = 836, CODE_FOR_fyl2xp1xf3_i387 = 837, CODE_FOR_fyl2xp1_extendsfxf3_i387 = 838, CODE_FOR_fyl2xp1_extenddfxf3_i387 = 839, CODE_FOR_fxtractxf3_i387 = 840, CODE_FOR_fxtract_extendsfxf3_i387 = 841, CODE_FOR_fxtract_extenddfxf3_i387 = 842, CODE_FOR_fscalexf4_i387 = 844, CODE_FOR_sse4_1_roundsf2 = 845, CODE_FOR_sse4_1_rounddf2 = 846, CODE_FOR_rintxf2 = 847, CODE_FOR_fistdi2 = 849, CODE_FOR_fistdi2_with_temp = 850, CODE_FOR_fisthi2 = 853, CODE_FOR_fistsi2 = 854, CODE_FOR_fisthi2_with_temp = 855, CODE_FOR_fistsi2_with_temp = 856, CODE_FOR_frndintxf2_floor = 857, CODE_FOR_frndintxf2_ceil = 858, CODE_FOR_frndintxf2_trunc = 859, CODE_FOR_frndintxf2_floor_i387 = 860, CODE_FOR_frndintxf2_ceil_i387 = 861, CODE_FOR_frndintxf2_trunc_i387 = 862, CODE_FOR_frndintxf2_mask_pm = 863, CODE_FOR_frndintxf2_mask_pm_i387 = 864, CODE_FOR_fistdi2_floor = 871, CODE_FOR_fistdi2_ceil = 872, CODE_FOR_fistdi2_floor_with_temp = 873, CODE_FOR_fistdi2_ceil_with_temp = 874, CODE_FOR_fisthi2_floor = 875, CODE_FOR_fisthi2_ceil = 876, CODE_FOR_fistsi2_floor = 877, CODE_FOR_fistsi2_ceil = 878, CODE_FOR_fisthi2_floor_with_temp = 879, CODE_FOR_fisthi2_ceil_with_temp = 880, CODE_FOR_fistsi2_floor_with_temp = 881, CODE_FOR_fistsi2_ceil_with_temp = 882, CODE_FOR_fxamsf2_i387 = 883, CODE_FOR_fxamdf2_i387 = 884, CODE_FOR_fxamxf2_i387 = 885, CODE_FOR_fxamsf2_i387_with_temp = 886, CODE_FOR_fxamdf2_i387_with_temp = 887, CODE_FOR_movmsk_df = 888, CODE_FOR_cld = 889, CODE_FOR_smaxsf3 = 939, CODE_FOR_sminsf3 = 940, CODE_FOR_smaxdf3 = 941, CODE_FOR_smindf3 = 942, CODE_FOR_pro_epilogue_adjust_stack_si_add = 947, CODE_FOR_pro_epilogue_adjust_stack_di_add = 948, CODE_FOR_pro_epilogue_adjust_stack_si_sub = 949, CODE_FOR_pro_epilogue_adjust_stack_di_sub = 950, CODE_FOR_allocate_stack_worker_probe_si = 951, CODE_FOR_allocate_stack_worker_probe_di = 952, CODE_FOR_adjust_stack_and_probesi = 953, CODE_FOR_adjust_stack_and_probedi = 954, CODE_FOR_probe_stack_rangesi = 955, CODE_FOR_probe_stack_rangedi = 956, #define CODE_FOR_nonlocal_goto_receiver CODE_FOR_nothing CODE_FOR_trap = 957, CODE_FOR_stack_protect_set_si = 961, CODE_FOR_stack_protect_set_di = 962, CODE_FOR_stack_tls_protect_set_si = 963, CODE_FOR_stack_tls_protect_set_di = 964, CODE_FOR_stack_protect_test_si = 965, CODE_FOR_stack_protect_test_di = 966, CODE_FOR_stack_tls_protect_test_si = 967, CODE_FOR_stack_tls_protect_test_di = 968, CODE_FOR_sse4_2_crc32qi = 969, CODE_FOR_sse4_2_crc32hi = 970, CODE_FOR_sse4_2_crc32si = 971, CODE_FOR_sse4_2_crc32di = 972, CODE_FOR_rdpmc = 973, CODE_FOR_rdpmc_rex64 = 974, CODE_FOR_rdtsc = 975, CODE_FOR_rdtsc_rex64 = 976, CODE_FOR_rdtscp = 977, CODE_FOR_rdtscp_rex64 = 978, CODE_FOR_fxsave = 979, CODE_FOR_fxsave64 = 980, CODE_FOR_fxrstor = 981, CODE_FOR_fxrstor64 = 982, CODE_FOR_xsave = 983, CODE_FOR_xsaveopt = 984, CODE_FOR_xsave_rex64 = 985, CODE_FOR_xsaveopt_rex64 = 986, CODE_FOR_xsave64 = 987, CODE_FOR_xsaveopt64 = 988, CODE_FOR_xrstor = 989, CODE_FOR_xrstor_rex64 = 990, CODE_FOR_xrstor64 = 991, CODE_FOR_fnstenv = 992, CODE_FOR_fldenv = 993, CODE_FOR_fnstsw = 994, CODE_FOR_fnclex = 995, CODE_FOR_lwp_slwpcbsi = 998, CODE_FOR_lwp_slwpcbdi = 999, CODE_FOR_rdfsbasesi = 1004, CODE_FOR_rdgsbasesi = 1005, CODE_FOR_rdfsbasedi = 1006, CODE_FOR_rdgsbasedi = 1007, CODE_FOR_wrfsbasesi = 1008, CODE_FOR_wrgsbasesi = 1009, CODE_FOR_wrfsbasedi = 1010, CODE_FOR_wrgsbasedi = 1011, CODE_FOR_rdrandhi_1 = 1012, CODE_FOR_rdrandsi_1 = 1013, CODE_FOR_rdranddi_1 = 1014, CODE_FOR_rdseedhi_1 = 1015, CODE_FOR_rdseedsi_1 = 1016, CODE_FOR_rdseeddi_1 = 1017, CODE_FOR_xbegin_1 = 1019, CODE_FOR_xend = 1020, CODE_FOR_xabort = 1021, CODE_FOR_xtest_1 = 1022, CODE_FOR_sse_movntq = 1028, CODE_FOR_mmx_rcpv2sf2 = 1036, CODE_FOR_mmx_rcpit1v2sf3 = 1037, CODE_FOR_mmx_rcpit2v2sf3 = 1038, CODE_FOR_mmx_rsqrtv2sf2 = 1039, CODE_FOR_mmx_rsqit1v2sf3 = 1040, CODE_FOR_mmx_haddv2sf3 = 1041, CODE_FOR_mmx_hsubv2sf3 = 1042, CODE_FOR_mmx_addsubv2sf3 = 1043, CODE_FOR_mmx_gtv2sf3 = 1045, CODE_FOR_mmx_gev2sf3 = 1046, CODE_FOR_mmx_pf2id = 1047, CODE_FOR_mmx_pf2iw = 1048, CODE_FOR_mmx_pi2fw = 1049, CODE_FOR_mmx_floatv2si2 = 1050, CODE_FOR_mmx_pswapdv2sf2 = 1051, CODE_FOR_mmx_ashrv4hi3 = 1082, CODE_FOR_mmx_ashrv2si3 = 1083, CODE_FOR_mmx_ashlv4hi3 = 1084, CODE_FOR_mmx_lshrv4hi3 = 1085, CODE_FOR_mmx_ashlv2si3 = 1086, CODE_FOR_mmx_lshrv2si3 = 1087, CODE_FOR_mmx_ashlv1di3 = 1088, CODE_FOR_mmx_lshrv1di3 = 1089, CODE_FOR_mmx_gtv8qi3 = 1093, CODE_FOR_mmx_gtv4hi3 = 1094, CODE_FOR_mmx_gtv2si3 = 1095, CODE_FOR_mmx_andnotv8qi3 = 1096, CODE_FOR_mmx_andnotv4hi3 = 1097, CODE_FOR_mmx_andnotv2si3 = 1098, CODE_FOR_mmx_packsswb = 1108, CODE_FOR_mmx_packssdw = 1109, CODE_FOR_mmx_packuswb = 1110, CODE_FOR_mmx_punpckhbw = 1111, CODE_FOR_mmx_punpcklbw = 1112, CODE_FOR_mmx_punpckhwd = 1113, CODE_FOR_mmx_punpcklwd = 1114, CODE_FOR_mmx_punpckhdq = 1115, CODE_FOR_mmx_punpckldq = 1116, CODE_FOR_mmx_pextrw = 1118, CODE_FOR_mmx_pshufw_1 = 1119, CODE_FOR_mmx_pswapdv2si2 = 1120, CODE_FOR_mmx_psadbw = 1129, CODE_FOR_mmx_pmovmskb = 1130, CODE_FOR_avx512f_loadv16si_mask = 1155, CODE_FOR_avx512f_loadv16sf_mask = 1156, CODE_FOR_avx512f_loadv8di_mask = 1157, CODE_FOR_avx512f_loadv8df_mask = 1158, CODE_FOR_avx512f_blendmv16si = 1159, CODE_FOR_avx512f_blendmv16sf = 1160, CODE_FOR_avx512f_blendmv8di = 1161, CODE_FOR_avx512f_blendmv8df = 1162, CODE_FOR_avx512f_storev16si_mask = 1163, CODE_FOR_avx512f_storev16sf_mask = 1164, CODE_FOR_avx512f_storev8di_mask = 1165, CODE_FOR_avx512f_storev8df_mask = 1166, CODE_FOR_sse2_movq128 = 1167, CODE_FOR_movdi_to_sse = 1168, CODE_FOR_avx512f_storeups512 = 1177, CODE_FOR_avx_storeups256 = 1178, CODE_FOR_sse_storeups = 1179, CODE_FOR_avx512f_storeupd512 = 1180, CODE_FOR_avx_storeupd256 = 1181, CODE_FOR_sse2_storeupd = 1182, CODE_FOR_avx512f_storeups512_mask = 1183, CODE_FOR_avx512f_storeupd512_mask = 1184, CODE_FOR_avx_storedquv32qi = 1191, CODE_FOR_sse2_storedquv16qi = 1192, CODE_FOR_avx512f_storedquv16si = 1193, CODE_FOR_avx512f_storedquv8di = 1194, CODE_FOR_avx512f_storedquv16si_mask = 1195, CODE_FOR_avx512f_storedquv8di_mask = 1196, CODE_FOR_avx_lddqu256 = 1197, CODE_FOR_sse3_lddqu = 1198, CODE_FOR_sse2_movntisi = 1199, CODE_FOR_sse2_movntidi = 1200, CODE_FOR_avx512f_movntv16sf = 1201, CODE_FOR_avx_movntv8sf = 1202, CODE_FOR_sse_movntv4sf = 1203, CODE_FOR_avx512f_movntv8df = 1204, CODE_FOR_avx_movntv4df = 1205, CODE_FOR_sse2_movntv2df = 1206, CODE_FOR_avx512f_movntv8di = 1207, CODE_FOR_avx_movntv4di = 1208, CODE_FOR_sse2_movntv2di = 1209, CODE_FOR_sse_vmaddv4sf3 = 1264, CODE_FOR_sse_vmaddv4sf3_round = 1265, CODE_FOR_sse_vmsubv4sf3 = 1266, CODE_FOR_sse_vmsubv4sf3_round = 1267, CODE_FOR_sse2_vmaddv2df3 = 1268, CODE_FOR_sse2_vmaddv2df3_round = 1269, CODE_FOR_sse2_vmsubv2df3 = 1270, CODE_FOR_sse2_vmsubv2df3_round = 1271, CODE_FOR_sse_vmmulv4sf3 = 1296, CODE_FOR_sse_vmmulv4sf3_round = 1297, CODE_FOR_sse_vmdivv4sf3 = 1298, CODE_FOR_sse_vmdivv4sf3_round = 1299, CODE_FOR_sse2_vmmulv2df3 = 1300, CODE_FOR_sse2_vmmulv2df3_round = 1301, CODE_FOR_sse2_vmdivv2df3 = 1302, CODE_FOR_sse2_vmdivv2df3_round = 1303, CODE_FOR_avx512f_divv16sf3 = 1304, CODE_FOR_avx512f_divv16sf3_round = 1305, CODE_FOR_avx512f_divv16sf3_mask = 1306, CODE_FOR_avx512f_divv16sf3_mask_round = 1307, CODE_FOR_avx_divv8sf3 = 1308, #define CODE_FOR_avx_divv8sf3_round CODE_FOR_nothing #define CODE_FOR_avx_divv8sf3_mask CODE_FOR_nothing #define CODE_FOR_avx_divv8sf3_mask_round CODE_FOR_nothing CODE_FOR_sse_divv4sf3 = 1309, #define CODE_FOR_sse_divv4sf3_round CODE_FOR_nothing #define CODE_FOR_sse_divv4sf3_mask CODE_FOR_nothing #define CODE_FOR_sse_divv4sf3_mask_round CODE_FOR_nothing CODE_FOR_avx512f_divv8df3 = 1310, CODE_FOR_avx512f_divv8df3_round = 1311, CODE_FOR_avx512f_divv8df3_mask = 1312, CODE_FOR_avx512f_divv8df3_mask_round = 1313, CODE_FOR_avx_divv4df3 = 1314, #define CODE_FOR_avx_divv4df3_round CODE_FOR_nothing #define CODE_FOR_avx_divv4df3_mask CODE_FOR_nothing #define CODE_FOR_avx_divv4df3_mask_round CODE_FOR_nothing CODE_FOR_sse2_divv2df3 = 1315, #define CODE_FOR_sse2_divv2df3_round CODE_FOR_nothing #define CODE_FOR_sse2_divv2df3_mask CODE_FOR_nothing #define CODE_FOR_sse2_divv2df3_mask_round CODE_FOR_nothing CODE_FOR_avx_rcpv8sf2 = 1316, CODE_FOR_sse_rcpv4sf2 = 1317, CODE_FOR_sse_vmrcpv4sf2 = 1318, CODE_FOR_rcp14v16sf_mask = 1320, CODE_FOR_rcp14v8df_mask = 1322, CODE_FOR_srcp14v4sf = 1323, CODE_FOR_srcp14v2df = 1324, CODE_FOR_avx512f_sqrtv16sf2 = 1325, CODE_FOR_avx512f_sqrtv16sf2_round = 1326, CODE_FOR_avx512f_sqrtv16sf2_mask = 1327, CODE_FOR_avx512f_sqrtv16sf2_mask_round = 1328, CODE_FOR_avx_sqrtv8sf2 = 1329, #define CODE_FOR_avx_sqrtv8sf2_round CODE_FOR_nothing #define CODE_FOR_avx_sqrtv8sf2_mask CODE_FOR_nothing #define CODE_FOR_avx_sqrtv8sf2_mask_round CODE_FOR_nothing CODE_FOR_sse_sqrtv4sf2 = 1330, #define CODE_FOR_sse_sqrtv4sf2_round CODE_FOR_nothing #define CODE_FOR_sse_sqrtv4sf2_mask CODE_FOR_nothing #define CODE_FOR_sse_sqrtv4sf2_mask_round CODE_FOR_nothing CODE_FOR_avx512f_sqrtv8df2 = 1331, CODE_FOR_avx512f_sqrtv8df2_round = 1332, CODE_FOR_avx512f_sqrtv8df2_mask = 1333, CODE_FOR_avx512f_sqrtv8df2_mask_round = 1334, CODE_FOR_avx_sqrtv4df2 = 1335, #define CODE_FOR_avx_sqrtv4df2_round CODE_FOR_nothing #define CODE_FOR_avx_sqrtv4df2_mask CODE_FOR_nothing #define CODE_FOR_avx_sqrtv4df2_mask_round CODE_FOR_nothing CODE_FOR_sse2_sqrtv2df2 = 1336, #define CODE_FOR_sse2_sqrtv2df2_round CODE_FOR_nothing #define CODE_FOR_sse2_sqrtv2df2_mask CODE_FOR_nothing #define CODE_FOR_sse2_sqrtv2df2_mask_round CODE_FOR_nothing CODE_FOR_sse_vmsqrtv4sf2 = 1337, CODE_FOR_sse_vmsqrtv4sf2_round = 1338, CODE_FOR_sse2_vmsqrtv2df2 = 1339, CODE_FOR_sse2_vmsqrtv2df2_round = 1340, CODE_FOR_avx_rsqrtv8sf2 = 1341, CODE_FOR_sse_rsqrtv4sf2 = 1342, CODE_FOR_rsqrt14v16sf_mask = 1344, CODE_FOR_rsqrt14v8df_mask = 1346, CODE_FOR_rsqrt14v4sf = 1347, CODE_FOR_rsqrt14v2df = 1348, CODE_FOR_sse_vmrsqrtv4sf2 = 1349, CODE_FOR_sse_vmsmaxv4sf3 = 1422, CODE_FOR_sse_vmsmaxv4sf3_round = 1423, CODE_FOR_sse_vmsminv4sf3 = 1424, CODE_FOR_sse_vmsminv4sf3_round = 1425, CODE_FOR_sse2_vmsmaxv2df3 = 1426, CODE_FOR_sse2_vmsmaxv2df3_round = 1427, CODE_FOR_sse2_vmsminv2df3 = 1428, CODE_FOR_sse2_vmsminv2df3_round = 1429, CODE_FOR_avx_addsubv4df3 = 1442, CODE_FOR_sse3_addsubv2df3 = 1443, CODE_FOR_avx_addsubv8sf3 = 1444, CODE_FOR_sse3_addsubv4sf3 = 1445, CODE_FOR_avx_haddv4df3 = 1446, CODE_FOR_avx_hsubv4df3 = 1447, CODE_FOR_sse3_hsubv2df3 = 1449, CODE_FOR_avx_haddv8sf3 = 1452, CODE_FOR_avx_hsubv8sf3 = 1453, CODE_FOR_sse3_haddv4sf3 = 1454, CODE_FOR_sse3_hsubv4sf3 = 1455, CODE_FOR_avx_cmpv8sf3 = 1456, CODE_FOR_avx_cmpv4sf3 = 1457, CODE_FOR_avx_cmpv4df3 = 1458, CODE_FOR_avx_cmpv2df3 = 1459, CODE_FOR_avx_vmcmpv4sf3 = 1460, CODE_FOR_avx_vmcmpv2df3 = 1461, CODE_FOR_avx_maskcmpv8sf3 = 1466, CODE_FOR_sse_maskcmpv4sf3 = 1467, CODE_FOR_avx_maskcmpv4df3 = 1468, CODE_FOR_sse2_maskcmpv2df3 = 1469, CODE_FOR_sse_vmmaskcmpv4sf3 = 1470, CODE_FOR_sse2_vmmaskcmpv2df3 = 1471, CODE_FOR_avx512f_cmpv16si3 = 1472, CODE_FOR_avx512f_cmpv16si3_mask = 1473, #define CODE_FOR_avx512f_cmpv16si3_round CODE_FOR_nothing #define CODE_FOR_avx512f_cmpv16si3_mask_round CODE_FOR_nothing CODE_FOR_avx512f_cmpv16sf3 = 1474, CODE_FOR_avx512f_cmpv16sf3_mask = 1475, CODE_FOR_avx512f_cmpv16sf3_round = 1476, CODE_FOR_avx512f_cmpv16sf3_mask_round = 1477, CODE_FOR_avx512f_cmpv8di3 = 1478, CODE_FOR_avx512f_cmpv8di3_mask = 1479, #define CODE_FOR_avx512f_cmpv8di3_round CODE_FOR_nothing #define CODE_FOR_avx512f_cmpv8di3_mask_round CODE_FOR_nothing CODE_FOR_avx512f_cmpv8df3 = 1480, CODE_FOR_avx512f_cmpv8df3_mask = 1481, CODE_FOR_avx512f_cmpv8df3_round = 1482, CODE_FOR_avx512f_cmpv8df3_mask_round = 1483, CODE_FOR_avx512f_ucmpv16si3 = 1484, CODE_FOR_avx512f_ucmpv16si3_mask = 1485, CODE_FOR_avx512f_ucmpv8di3 = 1486, CODE_FOR_avx512f_ucmpv8di3_mask = 1487, CODE_FOR_avx512f_vmcmpv4sf3 = 1488, CODE_FOR_avx512f_vmcmpv4sf3_round = 1489, CODE_FOR_avx512f_vmcmpv2df3 = 1490, CODE_FOR_avx512f_vmcmpv2df3_round = 1491, CODE_FOR_avx512f_vmcmpv4sf3_mask = 1492, CODE_FOR_avx512f_vmcmpv4sf3_mask_round = 1493, CODE_FOR_avx512f_vmcmpv2df3_mask = 1494, CODE_FOR_avx512f_vmcmpv2df3_mask_round = 1495, CODE_FOR_avx512f_maskcmpv16sf3 = 1496, CODE_FOR_avx512f_maskcmpv8sf3 = 1497, CODE_FOR_avx512f_maskcmpv4sf3 = 1498, CODE_FOR_avx512f_maskcmpv8df3 = 1499, CODE_FOR_avx512f_maskcmpv4df3 = 1500, CODE_FOR_avx512f_maskcmpv2df3 = 1501, CODE_FOR_sse_comi = 1502, CODE_FOR_sse_comi_round = 1503, CODE_FOR_sse2_comi = 1504, CODE_FOR_sse2_comi_round = 1505, CODE_FOR_sse_ucomi = 1506, CODE_FOR_sse_ucomi_round = 1507, CODE_FOR_sse2_ucomi = 1508, CODE_FOR_sse2_ucomi_round = 1509, CODE_FOR_avx512f_andnotv16sf3 = 1510, CODE_FOR_avx_andnotv8sf3 = 1511, CODE_FOR_sse_andnotv4sf3 = 1512, CODE_FOR_avx512f_andnotv8df3 = 1513, CODE_FOR_avx_andnotv4df3 = 1514, CODE_FOR_sse2_andnotv2df3 = 1515, CODE_FOR_avx512f_andv16sf = 1546, CODE_FOR_avx512f_xorv16sf = 1547, CODE_FOR_avx512f_andv8df = 1548, CODE_FOR_avx512f_xorv8df = 1549, #define CODE_FOR_fma_fmadd_v4sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v4sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v2df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v2df_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v8sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v8sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v4df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmadd_v4df_maskz_1_round CODE_FOR_nothing CODE_FOR_fma_fmadd_v16sf_maskz_1 = 1558, CODE_FOR_fma_fmadd_v16sf_maskz_1_round = 1559, CODE_FOR_fma_fmadd_v8df_maskz_1 = 1562, CODE_FOR_fma_fmadd_v8df_maskz_1_round = 1563, CODE_FOR_avx512f_fmadd_v16sf_mask = 1564, CODE_FOR_avx512f_fmadd_v16sf_mask_round = 1565, CODE_FOR_avx512f_fmadd_v8df_mask = 1566, CODE_FOR_avx512f_fmadd_v8df_mask_round = 1567, CODE_FOR_avx512f_fmadd_v16sf_mask3 = 1568, CODE_FOR_avx512f_fmadd_v16sf_mask3_round = 1569, CODE_FOR_avx512f_fmadd_v8df_mask3 = 1570, CODE_FOR_avx512f_fmadd_v8df_mask3_round = 1571, #define CODE_FOR_fma_fmsub_v4sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v4sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v2df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v2df_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v8sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v8sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v4df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsub_v4df_maskz_1_round CODE_FOR_nothing CODE_FOR_fma_fmsub_v16sf_maskz_1 = 1580, CODE_FOR_fma_fmsub_v16sf_maskz_1_round = 1581, CODE_FOR_fma_fmsub_v8df_maskz_1 = 1584, CODE_FOR_fma_fmsub_v8df_maskz_1_round = 1585, CODE_FOR_avx512f_fmsub_v16sf_mask = 1586, CODE_FOR_avx512f_fmsub_v16sf_mask_round = 1587, CODE_FOR_avx512f_fmsub_v8df_mask = 1588, CODE_FOR_avx512f_fmsub_v8df_mask_round = 1589, CODE_FOR_avx512f_fmsub_v16sf_mask3 = 1590, CODE_FOR_avx512f_fmsub_v16sf_mask3_round = 1591, CODE_FOR_avx512f_fmsub_v8df_mask3 = 1592, CODE_FOR_avx512f_fmsub_v8df_mask3_round = 1593, #define CODE_FOR_fma_fnmadd_v4sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v4sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v2df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v2df_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v8sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v8sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v4df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmadd_v4df_maskz_1_round CODE_FOR_nothing CODE_FOR_fma_fnmadd_v16sf_maskz_1 = 1602, CODE_FOR_fma_fnmadd_v16sf_maskz_1_round = 1603, CODE_FOR_fma_fnmadd_v8df_maskz_1 = 1606, CODE_FOR_fma_fnmadd_v8df_maskz_1_round = 1607, CODE_FOR_avx512f_fnmadd_v16sf_mask = 1608, CODE_FOR_avx512f_fnmadd_v16sf_mask_round = 1609, CODE_FOR_avx512f_fnmadd_v8df_mask = 1610, CODE_FOR_avx512f_fnmadd_v8df_mask_round = 1611, CODE_FOR_avx512f_fnmadd_v16sf_mask3 = 1612, CODE_FOR_avx512f_fnmadd_v16sf_mask3_round = 1613, CODE_FOR_avx512f_fnmadd_v8df_mask3 = 1614, CODE_FOR_avx512f_fnmadd_v8df_mask3_round = 1615, #define CODE_FOR_fma_fnmsub_v4sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v4sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v2df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v2df_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v8sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v8sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v4df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fnmsub_v4df_maskz_1_round CODE_FOR_nothing CODE_FOR_fma_fnmsub_v16sf_maskz_1 = 1624, CODE_FOR_fma_fnmsub_v16sf_maskz_1_round = 1625, CODE_FOR_fma_fnmsub_v8df_maskz_1 = 1628, CODE_FOR_fma_fnmsub_v8df_maskz_1_round = 1629, CODE_FOR_avx512f_fnmsub_v16sf_mask = 1630, CODE_FOR_avx512f_fnmsub_v16sf_mask_round = 1631, CODE_FOR_avx512f_fnmsub_v8df_mask = 1632, CODE_FOR_avx512f_fnmsub_v8df_mask_round = 1633, CODE_FOR_avx512f_fnmsub_v16sf_mask3 = 1634, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round = 1635, CODE_FOR_avx512f_fnmsub_v8df_mask3 = 1636, CODE_FOR_avx512f_fnmsub_v8df_mask3_round = 1637, #define CODE_FOR_fma_fmaddsub_v8sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v8sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v4sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v4sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v4df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v4df_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v2df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmaddsub_v2df_maskz_1_round CODE_FOR_nothing CODE_FOR_fma_fmaddsub_v16sf_maskz_1 = 1644, CODE_FOR_fma_fmaddsub_v16sf_maskz_1_round = 1645, CODE_FOR_fma_fmaddsub_v8df_maskz_1 = 1648, CODE_FOR_fma_fmaddsub_v8df_maskz_1_round = 1649, CODE_FOR_avx512f_fmaddsub_v16sf_mask = 1650, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round = 1651, CODE_FOR_avx512f_fmaddsub_v8df_mask = 1652, CODE_FOR_avx512f_fmaddsub_v8df_mask_round = 1653, CODE_FOR_avx512f_fmaddsub_v16sf_mask3 = 1654, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round = 1655, CODE_FOR_avx512f_fmaddsub_v8df_mask3 = 1656, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round = 1657, #define CODE_FOR_fma_fmsubadd_v8sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v8sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v4sf_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v4sf_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v4df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v4df_maskz_1_round CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v2df_maskz_1 CODE_FOR_nothing #define CODE_FOR_fma_fmsubadd_v2df_maskz_1_round CODE_FOR_nothing CODE_FOR_fma_fmsubadd_v16sf_maskz_1 = 1664, CODE_FOR_fma_fmsubadd_v16sf_maskz_1_round = 1665, CODE_FOR_fma_fmsubadd_v8df_maskz_1 = 1668, CODE_FOR_fma_fmsubadd_v8df_maskz_1_round = 1669, CODE_FOR_avx512f_fmsubadd_v16sf_mask = 1670, CODE_FOR_avx512f_fmsubadd_v16sf_mask_round = 1671, CODE_FOR_avx512f_fmsubadd_v8df_mask = 1672, CODE_FOR_avx512f_fmsubadd_v8df_mask_round = 1673, CODE_FOR_avx512f_fmsubadd_v16sf_mask3 = 1674, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round = 1675, CODE_FOR_avx512f_fmsubadd_v8df_mask3 = 1676, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round = 1677, CODE_FOR_sse_cvtpi2ps = 1702, CODE_FOR_sse_cvtps2pi = 1703, CODE_FOR_sse_cvttps2pi = 1704, CODE_FOR_sse_cvtsi2ss = 1705, CODE_FOR_sse_cvtsi2ss_round = 1706, CODE_FOR_sse_cvtsi2ssq = 1707, CODE_FOR_sse_cvtsi2ssq_round = 1708, CODE_FOR_sse_cvtss2si = 1709, CODE_FOR_sse_cvtss2si_round = 1710, CODE_FOR_sse_cvtss2si_2 = 1711, CODE_FOR_sse_cvtss2siq = 1712, CODE_FOR_sse_cvtss2siq_round = 1713, CODE_FOR_sse_cvtss2siq_2 = 1714, CODE_FOR_sse_cvttss2si = 1715, CODE_FOR_sse_cvttss2si_round = 1716, CODE_FOR_sse_cvttss2siq = 1717, CODE_FOR_sse_cvttss2siq_round = 1718, CODE_FOR_cvtusi2ss32 = 1719, CODE_FOR_cvtusi2ss32_round = 1720, CODE_FOR_cvtusi2sd32 = 1721, #define CODE_FOR_cvtusi2sd32_round CODE_FOR_nothing CODE_FOR_cvtusi2ss64 = 1722, CODE_FOR_cvtusi2ss64_round = 1723, CODE_FOR_cvtusi2sd64 = 1724, CODE_FOR_cvtusi2sd64_round = 1725, CODE_FOR_floatv16siv16sf2 = 1726, CODE_FOR_floatv16siv16sf2_round = 1727, CODE_FOR_floatv16siv16sf2_mask = 1728, CODE_FOR_floatv16siv16sf2_mask_round = 1729, CODE_FOR_floatv8siv8sf2 = 1730, #define CODE_FOR_floatv8siv8sf2_round CODE_FOR_nothing #define CODE_FOR_floatv8siv8sf2_mask CODE_FOR_nothing #define CODE_FOR_floatv8siv8sf2_mask_round CODE_FOR_nothing CODE_FOR_floatv4siv4sf2 = 1731, #define CODE_FOR_floatv4siv4sf2_round CODE_FOR_nothing #define CODE_FOR_floatv4siv4sf2_mask CODE_FOR_nothing #define CODE_FOR_floatv4siv4sf2_mask_round CODE_FOR_nothing CODE_FOR_ufloatv16siv16sf2 = 1732, CODE_FOR_ufloatv16siv16sf2_round = 1733, CODE_FOR_ufloatv16siv16sf2_mask = 1734, CODE_FOR_ufloatv16siv16sf2_mask_round = 1735, CODE_FOR_avx_fix_notruncv8sfv8si = 1736, CODE_FOR_sse2_fix_notruncv4sfv4si = 1737, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask = 1740, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round = 1741, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask = 1744, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round = 1745, CODE_FOR_fix_truncv16sfv16si2 = 1746, CODE_FOR_fix_truncv16sfv16si2_round = 1747, CODE_FOR_fix_truncv16sfv16si2_mask = 1748, CODE_FOR_fix_truncv16sfv16si2_mask_round = 1749, CODE_FOR_ufix_truncv16sfv16si2 = 1750, CODE_FOR_ufix_truncv16sfv16si2_round = 1751, CODE_FOR_ufix_truncv16sfv16si2_mask = 1752, CODE_FOR_ufix_truncv16sfv16si2_mask_round = 1753, CODE_FOR_fix_truncv8sfv8si2 = 1754, CODE_FOR_fix_truncv4sfv4si2 = 1755, CODE_FOR_sse2_cvtpi2pd = 1756, CODE_FOR_sse2_cvtpd2pi = 1757, CODE_FOR_sse2_cvttpd2pi = 1758, CODE_FOR_sse2_cvtsi2sd = 1759, CODE_FOR_sse2_cvtsi2sdq = 1760, CODE_FOR_sse2_cvtsi2sdq_round = 1761, CODE_FOR_avx512f_vcvtss2usi = 1762, CODE_FOR_avx512f_vcvtss2usi_round = 1763, CODE_FOR_avx512f_vcvtss2usiq = 1764, CODE_FOR_avx512f_vcvtss2usiq_round = 1765, CODE_FOR_avx512f_vcvttss2usi = 1766, CODE_FOR_avx512f_vcvttss2usi_round = 1767, CODE_FOR_avx512f_vcvttss2usiq = 1768, CODE_FOR_avx512f_vcvttss2usiq_round = 1769, CODE_FOR_avx512f_vcvtsd2usi = 1770, CODE_FOR_avx512f_vcvtsd2usi_round = 1771, CODE_FOR_avx512f_vcvtsd2usiq = 1772, CODE_FOR_avx512f_vcvtsd2usiq_round = 1773, CODE_FOR_avx512f_vcvttsd2usi = 1774, CODE_FOR_avx512f_vcvttsd2usi_round = 1775, CODE_FOR_avx512f_vcvttsd2usiq = 1776, CODE_FOR_avx512f_vcvttsd2usiq_round = 1777, CODE_FOR_sse2_cvtsd2si = 1778, CODE_FOR_sse2_cvtsd2si_round = 1779, CODE_FOR_sse2_cvtsd2si_2 = 1780, CODE_FOR_sse2_cvtsd2siq = 1781, CODE_FOR_sse2_cvtsd2siq_round = 1782, CODE_FOR_sse2_cvtsd2siq_2 = 1783, CODE_FOR_sse2_cvttsd2si = 1784, CODE_FOR_sse2_cvttsd2si_round = 1785, CODE_FOR_sse2_cvttsd2siq = 1786, CODE_FOR_sse2_cvttsd2siq_round = 1787, CODE_FOR_floatv8siv8df2 = 1788, CODE_FOR_floatv8siv8df2_mask = 1789, CODE_FOR_floatv4siv4df2 = 1790, #define CODE_FOR_floatv4siv4df2_mask CODE_FOR_nothing CODE_FOR_ufloatv8siv8df = 1791, CODE_FOR_ufloatv8siv8df_mask = 1792, CODE_FOR_avx512f_cvtdq2pd512_2 = 1793, CODE_FOR_avx_cvtdq2pd256_2 = 1794, CODE_FOR_sse2_cvtdq2pd = 1795, CODE_FOR_avx512f_cvtpd2dq512_mask = 1798, CODE_FOR_avx512f_cvtpd2dq512_mask_round = 1799, CODE_FOR_avx_cvtpd2dq256 = 1800, CODE_FOR_avx512f_ufix_notruncv8dfv8si = 1803, CODE_FOR_avx512f_ufix_notruncv8dfv8si_round = 1804, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask = 1805, CODE_FOR_avx512f_ufix_notruncv8dfv8si_mask_round = 1806, CODE_FOR_fix_truncv8dfv8si2 = 1807, CODE_FOR_fix_truncv8dfv8si2_round = 1808, CODE_FOR_fix_truncv8dfv8si2_mask = 1809, CODE_FOR_fix_truncv8dfv8si2_mask_round = 1810, CODE_FOR_ufix_truncv8dfv8si2 = 1811, CODE_FOR_ufix_truncv8dfv8si2_round = 1812, CODE_FOR_ufix_truncv8dfv8si2_mask = 1813, CODE_FOR_ufix_truncv8dfv8si2_mask_round = 1814, CODE_FOR_fix_truncv4dfv4si2 = 1815, CODE_FOR_sse2_cvtsd2ss = 1818, CODE_FOR_sse2_cvtsd2ss_round = 1819, CODE_FOR_sse2_cvtss2sd = 1820, CODE_FOR_sse2_cvtss2sd_round = 1821, CODE_FOR_avx512f_cvtpd2ps512_mask = 1824, CODE_FOR_avx512f_cvtpd2ps512_mask_round = 1825, CODE_FOR_avx_cvtpd2ps256 = 1826, CODE_FOR_avx512f_cvtps2pd512 = 1828, CODE_FOR_avx512f_cvtps2pd512_round = 1829, CODE_FOR_avx512f_cvtps2pd512_mask = 1830, CODE_FOR_avx512f_cvtps2pd512_mask_round = 1831, CODE_FOR_avx_cvtps2pd256 = 1832, #define CODE_FOR_avx_cvtps2pd256_round CODE_FOR_nothing #define CODE_FOR_avx_cvtps2pd256_mask CODE_FOR_nothing #define CODE_FOR_avx_cvtps2pd256_mask_round CODE_FOR_nothing CODE_FOR_vec_unpacks_lo_v16sf = 1834, CODE_FOR_sse2_cvtps2pd = 1835, CODE_FOR_sse_movhlps = 1836, CODE_FOR_sse_movlhps = 1837, CODE_FOR_avx512f_unpckhps512_mask = 1839, CODE_FOR_avx_unpckhps256 = 1840, CODE_FOR_vec_interleave_highv4sf = 1841, CODE_FOR_avx512f_unpcklps512_mask = 1843, CODE_FOR_avx_unpcklps256 = 1844, CODE_FOR_vec_interleave_lowv4sf = 1845, CODE_FOR_avx_movshdup256 = 1846, CODE_FOR_sse3_movshdup = 1847, CODE_FOR_avx512f_movshdup512_mask = 1849, CODE_FOR_avx_movsldup256 = 1850, CODE_FOR_sse3_movsldup = 1851, CODE_FOR_avx512f_movsldup512_mask = 1853, CODE_FOR_avx_shufps256_1 = 1854, CODE_FOR_sse_shufps_v4si = 1855, CODE_FOR_sse_shufps_v4sf = 1856, CODE_FOR_sse_storehps = 1857, CODE_FOR_sse_loadhps = 1858, CODE_FOR_sse_storelps = 1859, CODE_FOR_sse_loadlps = 1860, CODE_FOR_sse_movss = 1861, CODE_FOR_avx2_vec_dupv8sf = 1862, CODE_FOR_avx2_vec_dupv4sf = 1863, CODE_FOR_avx2_vec_dupv8sf_1 = 1864, CODE_FOR_vec_dupv4sf = 1865, CODE_FOR_vec_setv4si_0 = 1869, CODE_FOR_vec_setv4sf_0 = 1870, CODE_FOR_sse4_1_insertps = 1872, CODE_FOR_avx512f_vextractf32x4_1_maskm = 1876, CODE_FOR_avx512f_vextracti32x4_1_maskm = 1877, CODE_FOR_avx512f_vextractf32x4_1_mask = 1879, CODE_FOR_avx512f_vextracti32x4_1_mask = 1881, CODE_FOR_vec_extract_lo_v8df_maskm = 1882, CODE_FOR_vec_extract_lo_v8di_maskm = 1883, CODE_FOR_vec_extract_lo_v8df = 1884, CODE_FOR_vec_extract_lo_v8df_mask = 1885, CODE_FOR_vec_extract_lo_v8di = 1886, CODE_FOR_vec_extract_lo_v8di_mask = 1887, CODE_FOR_vec_extract_hi_v8df_maskm = 1888, CODE_FOR_vec_extract_hi_v8di_maskm = 1889, CODE_FOR_vec_extract_hi_v8df = 1890, CODE_FOR_vec_extract_hi_v8df_mask = 1891, CODE_FOR_vec_extract_hi_v8di = 1892, CODE_FOR_vec_extract_hi_v8di_mask = 1893, CODE_FOR_vec_extract_lo_v16sf = 1894, CODE_FOR_vec_extract_lo_v16si = 1895, CODE_FOR_vec_extract_hi_v16sf = 1896, CODE_FOR_vec_extract_hi_v16si = 1897, CODE_FOR_vec_extract_lo_v4di = 1898, CODE_FOR_vec_extract_lo_v4df = 1899, CODE_FOR_vec_extract_hi_v4di = 1900, CODE_FOR_vec_extract_hi_v4df = 1901, CODE_FOR_vec_extract_lo_v8si = 1902, CODE_FOR_vec_extract_lo_v8sf = 1903, CODE_FOR_vec_extract_hi_v8si = 1904, CODE_FOR_vec_extract_hi_v8sf = 1905, CODE_FOR_vec_extract_lo_v32hi = 1906, CODE_FOR_vec_extract_hi_v32hi = 1907, CODE_FOR_vec_extract_lo_v16hi = 1908, CODE_FOR_vec_extract_hi_v16hi = 1909, CODE_FOR_vec_extract_lo_v64qi = 1910, CODE_FOR_vec_extract_hi_v64qi = 1911, CODE_FOR_vec_extract_lo_v32qi = 1912, CODE_FOR_vec_extract_hi_v32qi = 1913, CODE_FOR_avx512f_unpckhpd512_mask = 1915, CODE_FOR_avx_unpckhpd256 = 1916, CODE_FOR_avx512f_vmscalefv4sf = 1922, CODE_FOR_avx512f_vmscalefv4sf_round = 1923, CODE_FOR_avx512f_vmscalefv2df = 1924, CODE_FOR_avx512f_vmscalefv2df_round = 1925, CODE_FOR_avx512f_scalefv16sf = 1926, CODE_FOR_avx512f_scalefv16sf_round = 1927, CODE_FOR_avx512f_scalefv16sf_mask = 1928, CODE_FOR_avx512f_scalefv16sf_mask_round = 1929, CODE_FOR_avx512f_scalefv8df = 1930, CODE_FOR_avx512f_scalefv8df_round = 1931, CODE_FOR_avx512f_scalefv8df_mask = 1932, CODE_FOR_avx512f_scalefv8df_mask_round = 1933, CODE_FOR_avx512f_vternlogv16si = 1934, CODE_FOR_avx512f_vternlogv16si_maskz_1 = 1935, CODE_FOR_avx512f_vternlogv8di = 1936, CODE_FOR_avx512f_vternlogv8di_maskz_1 = 1937, CODE_FOR_avx512f_vternlogv16si_mask = 1938, CODE_FOR_avx512f_vternlogv8di_mask = 1939, CODE_FOR_avx512f_getexpv16sf = 1940, CODE_FOR_avx512f_getexpv16sf_round = 1941, CODE_FOR_avx512f_getexpv16sf_mask = 1942, CODE_FOR_avx512f_getexpv16sf_mask_round = 1943, CODE_FOR_avx512f_getexpv8df = 1944, CODE_FOR_avx512f_getexpv8df_round = 1945, CODE_FOR_avx512f_getexpv8df_mask = 1946, CODE_FOR_avx512f_getexpv8df_mask_round = 1947, CODE_FOR_avx512f_sgetexpv4sf = 1948, CODE_FOR_avx512f_sgetexpv4sf_round = 1949, CODE_FOR_avx512f_sgetexpv2df = 1950, CODE_FOR_avx512f_sgetexpv2df_round = 1951, CODE_FOR_avx512f_alignv16si_mask = 1953, CODE_FOR_avx512f_alignv8di_mask = 1955, CODE_FOR_avx512f_fixupimmv16sf = 1956, CODE_FOR_avx512f_fixupimmv16sf_round = 1957, CODE_FOR_avx512f_fixupimmv16sf_maskz_1 = 1958, CODE_FOR_avx512f_fixupimmv16sf_maskz_1_round = 1959, CODE_FOR_avx512f_fixupimmv8df = 1960, CODE_FOR_avx512f_fixupimmv8df_round = 1961, CODE_FOR_avx512f_fixupimmv8df_maskz_1 = 1962, CODE_FOR_avx512f_fixupimmv8df_maskz_1_round = 1963, CODE_FOR_avx512f_fixupimmv16sf_mask = 1964, CODE_FOR_avx512f_fixupimmv16sf_mask_round = 1965, CODE_FOR_avx512f_fixupimmv8df_mask = 1966, CODE_FOR_avx512f_fixupimmv8df_mask_round = 1967, CODE_FOR_avx512f_sfixupimmv4sf = 1968, CODE_FOR_avx512f_sfixupimmv4sf_round = 1969, CODE_FOR_avx512f_sfixupimmv4sf_maskz_1 = 1970, CODE_FOR_avx512f_sfixupimmv4sf_maskz_1_round = 1971, CODE_FOR_avx512f_sfixupimmv2df = 1972, CODE_FOR_avx512f_sfixupimmv2df_round = 1973, CODE_FOR_avx512f_sfixupimmv2df_maskz_1 = 1974, CODE_FOR_avx512f_sfixupimmv2df_maskz_1_round = 1975, CODE_FOR_avx512f_sfixupimmv4sf_mask = 1976, CODE_FOR_avx512f_sfixupimmv4sf_mask_round = 1977, CODE_FOR_avx512f_sfixupimmv2df_mask = 1978, CODE_FOR_avx512f_sfixupimmv2df_mask_round = 1979, CODE_FOR_avx512f_rndscalev16sf = 1980, CODE_FOR_avx512f_rndscalev16sf_round = 1981, CODE_FOR_avx512f_rndscalev16sf_mask = 1982, CODE_FOR_avx512f_rndscalev16sf_mask_round = 1983, CODE_FOR_avx512f_rndscalev8df = 1984, CODE_FOR_avx512f_rndscalev8df_round = 1985, CODE_FOR_avx512f_rndscalev8df_mask = 1986, CODE_FOR_avx512f_rndscalev8df_mask_round = 1987, CODE_FOR_avx512f_rndscalev4sf = 1988, CODE_FOR_avx512f_rndscalev4sf_round = 1989, CODE_FOR_avx512f_rndscalev2df = 1990, CODE_FOR_avx512f_rndscalev2df_round = 1991, CODE_FOR_avx512f_shufps512_1 = 1992, CODE_FOR_avx512f_shufps512_1_mask = 1993, CODE_FOR_avx512f_shufpd512_1 = 1994, CODE_FOR_avx512f_shufpd512_1_mask = 1995, CODE_FOR_avx_shufpd256_1 = 1996, CODE_FOR_avx2_interleave_highv4di = 1997, CODE_FOR_avx512f_interleave_highv8di_mask = 1999, CODE_FOR_vec_interleave_highv2di = 2000, CODE_FOR_avx2_interleave_lowv4di = 2001, CODE_FOR_avx512f_interleave_lowv8di_mask = 2003, CODE_FOR_vec_interleave_lowv2di = 2004, CODE_FOR_sse2_shufpd_v2di = 2005, CODE_FOR_sse2_shufpd_v2df = 2006, CODE_FOR_sse2_storehpd = 2007, CODE_FOR_sse2_storelpd = 2009, CODE_FOR_sse2_loadhpd = 2011, CODE_FOR_sse2_loadlpd = 2012, CODE_FOR_sse2_movsd = 2013, CODE_FOR_vec_dupv2df = 2014, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask = 2028, CODE_FOR_avx512f_truncatev16siv16qi2_mask = 2029, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask = 2030, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask = 2031, CODE_FOR_avx512f_truncatev16siv16hi2_mask = 2032, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask = 2033, CODE_FOR_avx512f_ss_truncatev8div8si2_mask = 2034, CODE_FOR_avx512f_truncatev8div8si2_mask = 2035, CODE_FOR_avx512f_us_truncatev8div8si2_mask = 2036, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask = 2037, CODE_FOR_avx512f_truncatev8div8hi2_mask = 2038, CODE_FOR_avx512f_us_truncatev8div8hi2_mask = 2039, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask = 2046, CODE_FOR_avx512f_truncatev8div16qi2_mask = 2047, CODE_FOR_avx512f_us_truncatev8div16qi2_mask = 2048, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store = 2049, CODE_FOR_avx512f_truncatev8div16qi2_mask_store = 2050, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store = 2051, CODE_FOR_ashrv16hi3 = 2128, CODE_FOR_ashrv8hi3 = 2129, CODE_FOR_ashrv8si3 = 2130, CODE_FOR_ashrv4si3 = 2131, CODE_FOR_ashrv16si3 = 2132, CODE_FOR_ashrv16si3_mask = 2133, CODE_FOR_ashrv8di3 = 2134, CODE_FOR_ashrv8di3_mask = 2135, CODE_FOR_ashlv16hi3 = 2136, CODE_FOR_lshrv16hi3 = 2137, CODE_FOR_ashlv8hi3 = 2138, CODE_FOR_lshrv8hi3 = 2139, CODE_FOR_ashlv8si3 = 2140, CODE_FOR_lshrv8si3 = 2141, CODE_FOR_ashlv4si3 = 2142, CODE_FOR_lshrv4si3 = 2143, CODE_FOR_ashlv4di3 = 2144, CODE_FOR_lshrv4di3 = 2145, CODE_FOR_ashlv2di3 = 2146, CODE_FOR_lshrv2di3 = 2147, CODE_FOR_ashlv16si3 = 2148, CODE_FOR_ashlv16si3_mask = 2149, CODE_FOR_lshrv16si3 = 2150, CODE_FOR_lshrv16si3_mask = 2151, CODE_FOR_ashlv8di3 = 2152, CODE_FOR_ashlv8di3_mask = 2153, CODE_FOR_lshrv8di3 = 2154, CODE_FOR_lshrv8di3_mask = 2155, CODE_FOR_avx2_ashlv2ti3 = 2156, CODE_FOR_sse2_ashlv1ti3 = 2157, CODE_FOR_avx2_lshrv2ti3 = 2158, CODE_FOR_sse2_lshrv1ti3 = 2159, CODE_FOR_avx512f_rolvv16si = 2160, CODE_FOR_avx512f_rolvv16si_mask = 2161, CODE_FOR_avx512f_rorvv16si = 2162, CODE_FOR_avx512f_rorvv16si_mask = 2163, CODE_FOR_avx512f_rolvv8di = 2164, CODE_FOR_avx512f_rolvv8di_mask = 2165, CODE_FOR_avx512f_rorvv8di = 2166, CODE_FOR_avx512f_rorvv8di_mask = 2167, CODE_FOR_avx512f_rolv16si = 2168, CODE_FOR_avx512f_rolv16si_mask = 2169, CODE_FOR_avx512f_rorv16si = 2170, CODE_FOR_avx512f_rorv16si_mask = 2171, CODE_FOR_avx512f_rolv8di = 2172, CODE_FOR_avx512f_rolv8di_mask = 2173, CODE_FOR_avx512f_rorv8di = 2174, CODE_FOR_avx512f_rorv8di_mask = 2175, CODE_FOR_avx512f_eqv16si3_1 = 2260, CODE_FOR_avx512f_eqv16si3_mask_1 = 2261, CODE_FOR_avx512f_eqv8di3_1 = 2262, CODE_FOR_avx512f_eqv8di3_mask_1 = 2263, CODE_FOR_sse4_2_gtv2di3 = 2268, CODE_FOR_avx2_gtv32qi3 = 2269, CODE_FOR_avx2_gtv16hi3 = 2270, CODE_FOR_avx2_gtv8si3 = 2271, CODE_FOR_avx2_gtv4di3 = 2272, CODE_FOR_avx512f_gtv16si3 = 2273, CODE_FOR_avx512f_gtv16si3_mask = 2274, CODE_FOR_avx512f_gtv8di3 = 2275, CODE_FOR_avx512f_gtv8di3_mask = 2276, CODE_FOR_sse2_gtv16qi3 = 2277, CODE_FOR_sse2_gtv8hi3 = 2278, CODE_FOR_sse2_gtv4si3 = 2279, CODE_FOR_andv16si3_mask = 2293, CODE_FOR_iorv16si3_mask = 2295, CODE_FOR_xorv16si3_mask = 2297, CODE_FOR_andv8di3_mask = 2299, CODE_FOR_iorv8di3_mask = 2301, CODE_FOR_xorv8di3_mask = 2303, #define CODE_FOR_andv16qi3_mask CODE_FOR_nothing #define CODE_FOR_iorv16qi3_mask CODE_FOR_nothing #define CODE_FOR_xorv16qi3_mask CODE_FOR_nothing #define CODE_FOR_andv16hi3_mask CODE_FOR_nothing #define CODE_FOR_iorv16hi3_mask CODE_FOR_nothing #define CODE_FOR_xorv16hi3_mask CODE_FOR_nothing #define CODE_FOR_andv8hi3_mask CODE_FOR_nothing #define CODE_FOR_iorv8hi3_mask CODE_FOR_nothing #define CODE_FOR_xorv8hi3_mask CODE_FOR_nothing #define CODE_FOR_andv8si3_mask CODE_FOR_nothing #define CODE_FOR_iorv8si3_mask CODE_FOR_nothing #define CODE_FOR_xorv8si3_mask CODE_FOR_nothing #define CODE_FOR_andv4si3_mask CODE_FOR_nothing #define CODE_FOR_iorv4si3_mask CODE_FOR_nothing #define CODE_FOR_xorv4si3_mask CODE_FOR_nothing #define CODE_FOR_andv4di3_mask CODE_FOR_nothing #define CODE_FOR_iorv4di3_mask CODE_FOR_nothing #define CODE_FOR_xorv4di3_mask CODE_FOR_nothing #define CODE_FOR_andv2di3_mask CODE_FOR_nothing #define CODE_FOR_iorv2di3_mask CODE_FOR_nothing #define CODE_FOR_xorv2di3_mask CODE_FOR_nothing CODE_FOR_avx512f_testmv16si3 = 2328, CODE_FOR_avx512f_testmv16si3_mask = 2329, CODE_FOR_avx512f_testmv8di3 = 2330, CODE_FOR_avx512f_testmv8di3_mask = 2331, CODE_FOR_avx512f_testnmv16si3 = 2332, CODE_FOR_avx512f_testnmv16si3_mask = 2333, CODE_FOR_avx512f_testnmv8di3 = 2334, CODE_FOR_avx512f_testnmv8di3_mask = 2335, CODE_FOR_avx2_packsswb = 2336, CODE_FOR_sse2_packsswb = 2337, CODE_FOR_avx2_packssdw = 2338, CODE_FOR_sse2_packssdw = 2339, CODE_FOR_avx2_packuswb = 2340, CODE_FOR_sse2_packuswb = 2341, CODE_FOR_avx2_interleave_highv32qi = 2342, CODE_FOR_vec_interleave_highv16qi = 2343, CODE_FOR_avx2_interleave_lowv32qi = 2344, CODE_FOR_vec_interleave_lowv16qi = 2345, CODE_FOR_avx2_interleave_highv16hi = 2346, CODE_FOR_vec_interleave_highv8hi = 2347, CODE_FOR_avx2_interleave_lowv16hi = 2348, CODE_FOR_vec_interleave_lowv8hi = 2349, CODE_FOR_avx2_interleave_highv8si = 2350, CODE_FOR_avx512f_interleave_highv16si_mask = 2352, CODE_FOR_vec_interleave_highv4si = 2353, CODE_FOR_avx2_interleave_lowv8si = 2354, CODE_FOR_avx512f_interleave_lowv16si_mask = 2356, CODE_FOR_vec_interleave_lowv4si = 2357, CODE_FOR_sse4_1_pinsrb = 2358, CODE_FOR_sse2_pinsrw = 2359, CODE_FOR_sse4_1_pinsrd = 2360, CODE_FOR_sse4_1_pinsrq = 2361, CODE_FOR_avx512f_vinsertf32x4_1_mask = 2363, CODE_FOR_avx512f_vinserti32x4_1_mask = 2365, CODE_FOR_vec_set_lo_v8df = 2366, CODE_FOR_vec_set_lo_v8df_mask = 2367, CODE_FOR_vec_set_lo_v8di = 2368, CODE_FOR_vec_set_lo_v8di_mask = 2369, CODE_FOR_vec_set_hi_v8df = 2370, CODE_FOR_vec_set_hi_v8df_mask = 2371, CODE_FOR_vec_set_hi_v8di = 2372, CODE_FOR_vec_set_hi_v8di_mask = 2373, CODE_FOR_avx512f_shuf_f64x2_1 = 2374, CODE_FOR_avx512f_shuf_f64x2_1_mask = 2375, CODE_FOR_avx512f_shuf_i64x2_1 = 2376, CODE_FOR_avx512f_shuf_i64x2_1_mask = 2377, CODE_FOR_avx512f_shuf_f32x4_1 = 2378, CODE_FOR_avx512f_shuf_f32x4_1_mask = 2379, CODE_FOR_avx512f_shuf_i32x4_1 = 2380, CODE_FOR_avx512f_shuf_i32x4_1_mask = 2381, CODE_FOR_avx512f_pshufd_1 = 2382, CODE_FOR_avx512f_pshufd_1_mask = 2383, CODE_FOR_avx2_pshufd_1 = 2384, CODE_FOR_sse2_pshufd_1 = 2385, CODE_FOR_avx2_pshuflw_1 = 2386, CODE_FOR_sse2_pshuflw_1 = 2387, CODE_FOR_avx2_pshufhw_1 = 2388, CODE_FOR_sse2_pshufhw_1 = 2389, CODE_FOR_sse2_loadld = 2390, CODE_FOR_vec_concatv2di = 2414, CODE_FOR_avx2_psadbw = 2419, CODE_FOR_sse2_psadbw = 2420, CODE_FOR_avx_movmskps256 = 2421, CODE_FOR_sse_movmskps = 2422, CODE_FOR_avx_movmskpd256 = 2423, CODE_FOR_sse2_movmskpd = 2424, CODE_FOR_avx2_pmovmskb = 2425, CODE_FOR_sse2_pmovmskb = 2426, CODE_FOR_sse_ldmxcsr = 2429, CODE_FOR_sse_stmxcsr = 2430, CODE_FOR_sse2_clflush = 2431, CODE_FOR_sse3_mwait = 2432, CODE_FOR_sse3_monitor_si = 2433, CODE_FOR_sse3_monitor_di = 2434, CODE_FOR_avx2_phaddwv16hi3 = 2435, CODE_FOR_avx2_phaddswv16hi3 = 2436, CODE_FOR_avx2_phsubwv16hi3 = 2437, CODE_FOR_avx2_phsubswv16hi3 = 2438, CODE_FOR_ssse3_phaddwv8hi3 = 2439, CODE_FOR_ssse3_phaddswv8hi3 = 2440, CODE_FOR_ssse3_phsubwv8hi3 = 2441, CODE_FOR_ssse3_phsubswv8hi3 = 2442, CODE_FOR_ssse3_phaddwv4hi3 = 2443, CODE_FOR_ssse3_phaddswv4hi3 = 2444, CODE_FOR_ssse3_phsubwv4hi3 = 2445, CODE_FOR_ssse3_phsubswv4hi3 = 2446, CODE_FOR_avx2_phadddv8si3 = 2447, CODE_FOR_avx2_phsubdv8si3 = 2448, CODE_FOR_ssse3_phadddv4si3 = 2449, CODE_FOR_ssse3_phsubdv4si3 = 2450, CODE_FOR_ssse3_phadddv2si3 = 2451, CODE_FOR_ssse3_phsubdv2si3 = 2452, CODE_FOR_avx2_pmaddubsw256 = 2453, CODE_FOR_ssse3_pmaddubsw128 = 2454, CODE_FOR_ssse3_pmaddubsw = 2455, CODE_FOR_avx2_pshufbv32qi3 = 2459, CODE_FOR_ssse3_pshufbv16qi3 = 2460, CODE_FOR_ssse3_pshufbv8qi3 = 2461, CODE_FOR_avx2_psignv32qi3 = 2462, CODE_FOR_ssse3_psignv16qi3 = 2463, CODE_FOR_avx2_psignv16hi3 = 2464, CODE_FOR_ssse3_psignv8hi3 = 2465, CODE_FOR_avx2_psignv8si3 = 2466, CODE_FOR_ssse3_psignv4si3 = 2467, CODE_FOR_ssse3_psignv8qi3 = 2468, CODE_FOR_ssse3_psignv4hi3 = 2469, CODE_FOR_ssse3_psignv2si3 = 2470, CODE_FOR_avx2_palignrv2ti = 2471, CODE_FOR_ssse3_palignrti = 2472, CODE_FOR_ssse3_palignrdi = 2473, #define CODE_FOR_absv16qi2_mask CODE_FOR_nothing #define CODE_FOR_absv16hi2_mask CODE_FOR_nothing #define CODE_FOR_absv8hi2_mask CODE_FOR_nothing CODE_FOR_absv16si2_mask = 2479, #define CODE_FOR_absv8si2_mask CODE_FOR_nothing #define CODE_FOR_absv4si2_mask CODE_FOR_nothing CODE_FOR_absv8di2_mask = 2483, CODE_FOR_absv8qi2 = 2484, CODE_FOR_absv4hi2 = 2485, CODE_FOR_absv2si2 = 2486, CODE_FOR_sse4a_movntsf = 2487, CODE_FOR_sse4a_movntdf = 2488, CODE_FOR_sse4a_vmmovntv4sf = 2489, CODE_FOR_sse4a_vmmovntv2df = 2490, CODE_FOR_sse4a_extrqi = 2491, CODE_FOR_sse4a_extrq = 2492, CODE_FOR_sse4a_insertqi = 2493, CODE_FOR_sse4a_insertq = 2494, CODE_FOR_avx_blendps256 = 2495, CODE_FOR_sse4_1_blendps = 2496, CODE_FOR_avx_blendpd256 = 2497, CODE_FOR_sse4_1_blendpd = 2498, CODE_FOR_avx_blendvps256 = 2499, CODE_FOR_sse4_1_blendvps = 2500, CODE_FOR_avx_blendvpd256 = 2501, CODE_FOR_sse4_1_blendvpd = 2502, CODE_FOR_avx_dpps256 = 2503, CODE_FOR_sse4_1_dpps = 2504, CODE_FOR_avx_dppd256 = 2505, CODE_FOR_sse4_1_dppd = 2506, CODE_FOR_avx512f_movntdqa = 2507, CODE_FOR_avx2_movntdqa = 2508, CODE_FOR_sse4_1_movntdqa = 2509, CODE_FOR_avx2_mpsadbw = 2510, CODE_FOR_sse4_1_mpsadbw = 2511, CODE_FOR_avx2_packusdw = 2512, CODE_FOR_sse4_1_packusdw = 2513, CODE_FOR_avx2_pblendvb = 2514, CODE_FOR_sse4_1_pblendvb = 2515, CODE_FOR_sse4_1_pblendw = 2516, CODE_FOR_avx2_pblenddv8si = 2518, CODE_FOR_avx2_pblenddv4si = 2519, CODE_FOR_sse4_1_phminposuw = 2520, CODE_FOR_avx2_sign_extendv16qiv16hi2 = 2521, CODE_FOR_avx2_zero_extendv16qiv16hi2 = 2522, CODE_FOR_sse4_1_sign_extendv8qiv8hi2 = 2523, CODE_FOR_sse4_1_zero_extendv8qiv8hi2 = 2524, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask = 2526, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask = 2528, CODE_FOR_avx2_sign_extendv8qiv8si2 = 2529, CODE_FOR_avx2_zero_extendv8qiv8si2 = 2530, CODE_FOR_sse4_1_sign_extendv4qiv4si2 = 2531, CODE_FOR_sse4_1_zero_extendv4qiv4si2 = 2532, CODE_FOR_avx512f_sign_extendv16hiv16si2 = 2533, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask = 2534, CODE_FOR_avx512f_zero_extendv16hiv16si2 = 2535, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask = 2536, CODE_FOR_avx2_sign_extendv8hiv8si2 = 2537, CODE_FOR_avx2_zero_extendv8hiv8si2 = 2538, CODE_FOR_sse4_1_sign_extendv4hiv4si2 = 2539, CODE_FOR_sse4_1_zero_extendv4hiv4si2 = 2540, CODE_FOR_avx512f_sign_extendv8qiv8di2 = 2541, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask = 2542, CODE_FOR_avx512f_zero_extendv8qiv8di2 = 2543, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask = 2544, CODE_FOR_avx2_sign_extendv4qiv4di2 = 2545, CODE_FOR_avx2_zero_extendv4qiv4di2 = 2546, CODE_FOR_sse4_1_sign_extendv2qiv2di2 = 2547, CODE_FOR_sse4_1_zero_extendv2qiv2di2 = 2548, CODE_FOR_avx512f_sign_extendv8hiv8di2 = 2549, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask = 2550, CODE_FOR_avx512f_zero_extendv8hiv8di2 = 2551, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask = 2552, CODE_FOR_avx2_sign_extendv4hiv4di2 = 2553, CODE_FOR_avx2_zero_extendv4hiv4di2 = 2554, CODE_FOR_sse4_1_sign_extendv2hiv2di2 = 2555, CODE_FOR_sse4_1_zero_extendv2hiv2di2 = 2556, CODE_FOR_avx512f_sign_extendv8siv8di2 = 2557, CODE_FOR_avx512f_sign_extendv8siv8di2_mask = 2558, CODE_FOR_avx512f_zero_extendv8siv8di2 = 2559, CODE_FOR_avx512f_zero_extendv8siv8di2_mask = 2560, CODE_FOR_avx2_sign_extendv4siv4di2 = 2561, CODE_FOR_avx2_zero_extendv4siv4di2 = 2562, CODE_FOR_sse4_1_sign_extendv2siv2di2 = 2563, CODE_FOR_sse4_1_zero_extendv2siv2di2 = 2564, CODE_FOR_avx_vtestps256 = 2565, CODE_FOR_avx_vtestps = 2566, CODE_FOR_avx_vtestpd256 = 2567, CODE_FOR_avx_vtestpd = 2568, CODE_FOR_avx_ptest256 = 2569, CODE_FOR_sse4_1_ptest = 2570, CODE_FOR_avx_roundps256 = 2571, CODE_FOR_sse4_1_roundps = 2572, CODE_FOR_avx_roundpd256 = 2573, CODE_FOR_sse4_1_roundpd = 2574, CODE_FOR_sse4_1_roundss = 2575, CODE_FOR_sse4_1_roundsd = 2576, CODE_FOR_sse4_2_pcmpestr = 2577, CODE_FOR_sse4_2_pcmpestri = 2579, CODE_FOR_sse4_2_pcmpestrm = 2580, CODE_FOR_sse4_2_pcmpestr_cconly = 2581, CODE_FOR_sse4_2_pcmpistr = 2582, CODE_FOR_sse4_2_pcmpistri = 2584, CODE_FOR_sse4_2_pcmpistrm = 2585, CODE_FOR_sse4_2_pcmpistr_cconly = 2586, CODE_FOR_avx512er_exp2v16sf = 2619, CODE_FOR_avx512er_exp2v16sf_round = 2620, CODE_FOR_avx512er_exp2v16sf_mask = 2621, CODE_FOR_avx512er_exp2v16sf_mask_round = 2622, CODE_FOR_avx512er_exp2v8df = 2623, CODE_FOR_avx512er_exp2v8df_round = 2624, CODE_FOR_avx512er_exp2v8df_mask = 2625, CODE_FOR_avx512er_exp2v8df_mask_round = 2626, CODE_FOR_avx512er_rcp28v16sf_mask = 2629, CODE_FOR_avx512er_rcp28v16sf_mask_round = 2630, CODE_FOR_avx512er_rcp28v8df_mask = 2633, CODE_FOR_avx512er_rcp28v8df_mask_round = 2634, CODE_FOR_avx512er_vmrcp28v4sf = 2635, CODE_FOR_avx512er_vmrcp28v4sf_round = 2636, CODE_FOR_avx512er_vmrcp28v2df = 2637, CODE_FOR_avx512er_vmrcp28v2df_round = 2638, CODE_FOR_avx512er_rsqrt28v16sf_mask = 2641, CODE_FOR_avx512er_rsqrt28v16sf_mask_round = 2642, CODE_FOR_avx512er_rsqrt28v8df_mask = 2645, CODE_FOR_avx512er_rsqrt28v8df_mask_round = 2646, CODE_FOR_avx512er_vmrsqrt28v4sf = 2647, CODE_FOR_avx512er_vmrsqrt28v4sf_round = 2648, CODE_FOR_avx512er_vmrsqrt28v2df = 2649, CODE_FOR_avx512er_vmrsqrt28v2df_round = 2650, CODE_FOR_xop_pmacsww = 2651, CODE_FOR_xop_pmacssww = 2652, CODE_FOR_xop_pmacsdd = 2653, CODE_FOR_xop_pmacssdd = 2654, CODE_FOR_xop_pmacsdql = 2655, CODE_FOR_xop_pmacssdql = 2656, CODE_FOR_xop_pmacsdqh = 2657, CODE_FOR_xop_pmacssdqh = 2658, CODE_FOR_xop_pmacswd = 2659, CODE_FOR_xop_pmacsswd = 2660, CODE_FOR_xop_pmadcswd = 2661, CODE_FOR_xop_pmadcsswd = 2662, CODE_FOR_xop_pcmov_v32qi256 = 2663, CODE_FOR_xop_pcmov_v16qi = 2664, CODE_FOR_xop_pcmov_v16hi256 = 2665, CODE_FOR_xop_pcmov_v8hi = 2666, CODE_FOR_xop_pcmov_v16si512 = 2667, CODE_FOR_xop_pcmov_v8si256 = 2668, CODE_FOR_xop_pcmov_v4si = 2669, CODE_FOR_xop_pcmov_v8di512 = 2670, CODE_FOR_xop_pcmov_v4di256 = 2671, CODE_FOR_xop_pcmov_v2di = 2672, CODE_FOR_xop_pcmov_v16sf512 = 2673, CODE_FOR_xop_pcmov_v8sf256 = 2674, CODE_FOR_xop_pcmov_v4sf = 2675, CODE_FOR_xop_pcmov_v8df512 = 2676, CODE_FOR_xop_pcmov_v4df256 = 2677, CODE_FOR_xop_pcmov_v2df = 2678, CODE_FOR_xop_phaddbw = 2679, CODE_FOR_xop_phaddubw = 2680, CODE_FOR_xop_phaddbd = 2681, CODE_FOR_xop_phaddubd = 2682, CODE_FOR_xop_phaddbq = 2683, CODE_FOR_xop_phaddubq = 2684, CODE_FOR_xop_phaddwd = 2685, CODE_FOR_xop_phadduwd = 2686, CODE_FOR_xop_phaddwq = 2687, CODE_FOR_xop_phadduwq = 2688, CODE_FOR_xop_phadddq = 2689, CODE_FOR_xop_phaddudq = 2690, CODE_FOR_xop_phsubbw = 2691, CODE_FOR_xop_phsubwd = 2692, CODE_FOR_xop_phsubdq = 2693, CODE_FOR_xop_pperm = 2694, CODE_FOR_xop_pperm_pack_v2di_v4si = 2695, CODE_FOR_xop_pperm_pack_v4si_v8hi = 2696, CODE_FOR_xop_pperm_pack_v8hi_v16qi = 2697, CODE_FOR_xop_rotlv16qi3 = 2698, CODE_FOR_xop_rotlv8hi3 = 2699, CODE_FOR_xop_rotlv4si3 = 2700, CODE_FOR_xop_rotlv2di3 = 2701, CODE_FOR_xop_rotrv16qi3 = 2702, CODE_FOR_xop_rotrv8hi3 = 2703, CODE_FOR_xop_rotrv4si3 = 2704, CODE_FOR_xop_rotrv2di3 = 2705, CODE_FOR_xop_vrotlv16qi3 = 2706, CODE_FOR_xop_vrotlv8hi3 = 2707, CODE_FOR_xop_vrotlv4si3 = 2708, CODE_FOR_xop_vrotlv2di3 = 2709, CODE_FOR_xop_shav16qi3 = 2710, CODE_FOR_xop_shav8hi3 = 2711, CODE_FOR_xop_shav4si3 = 2712, CODE_FOR_xop_shav2di3 = 2713, CODE_FOR_xop_shlv16qi3 = 2714, CODE_FOR_xop_shlv8hi3 = 2715, CODE_FOR_xop_shlv4si3 = 2716, CODE_FOR_xop_shlv2di3 = 2717, CODE_FOR_xop_frczsf2 = 2718, CODE_FOR_xop_frczdf2 = 2719, CODE_FOR_xop_frczv4sf2 = 2720, CODE_FOR_xop_frczv2df2 = 2721, CODE_FOR_xop_frczv8sf2 = 2722, CODE_FOR_xop_frczv4df2 = 2723, CODE_FOR_xop_frczv16sf2 = 2724, CODE_FOR_xop_frczv8df2 = 2725, CODE_FOR_xop_maskcmpv16qi3 = 2728, CODE_FOR_xop_maskcmpv8hi3 = 2729, CODE_FOR_xop_maskcmpv4si3 = 2730, CODE_FOR_xop_maskcmpv2di3 = 2731, CODE_FOR_xop_maskcmp_unsv16qi3 = 2732, CODE_FOR_xop_maskcmp_unsv8hi3 = 2733, CODE_FOR_xop_maskcmp_unsv4si3 = 2734, CODE_FOR_xop_maskcmp_unsv2di3 = 2735, CODE_FOR_xop_maskcmp_uns2v16qi3 = 2736, CODE_FOR_xop_maskcmp_uns2v8hi3 = 2737, CODE_FOR_xop_maskcmp_uns2v4si3 = 2738, CODE_FOR_xop_maskcmp_uns2v2di3 = 2739, CODE_FOR_xop_pcom_tfv16qi3 = 2740, CODE_FOR_xop_pcom_tfv8hi3 = 2741, CODE_FOR_xop_pcom_tfv4si3 = 2742, CODE_FOR_xop_pcom_tfv2di3 = 2743, CODE_FOR_xop_vpermil2v8sf3 = 2744, CODE_FOR_xop_vpermil2v4sf3 = 2745, CODE_FOR_xop_vpermil2v4df3 = 2746, CODE_FOR_xop_vpermil2v2df3 = 2747, CODE_FOR_aesenc = 2748, CODE_FOR_aesenclast = 2749, CODE_FOR_aesdec = 2750, CODE_FOR_aesdeclast = 2751, CODE_FOR_aesimc = 2752, CODE_FOR_aeskeygenassist = 2753, CODE_FOR_pclmulqdq = 2754, CODE_FOR_avx_vzeroupper = 2756, CODE_FOR_avx2_pbroadcastv16si = 2757, CODE_FOR_avx2_pbroadcastv8di = 2758, CODE_FOR_avx2_pbroadcastv32qi = 2759, CODE_FOR_avx2_pbroadcastv16qi = 2760, CODE_FOR_avx2_pbroadcastv16hi = 2761, CODE_FOR_avx2_pbroadcastv8hi = 2762, CODE_FOR_avx2_pbroadcastv8si = 2763, CODE_FOR_avx2_pbroadcastv4si = 2764, CODE_FOR_avx2_pbroadcastv4di = 2765, CODE_FOR_avx2_pbroadcastv2di = 2766, CODE_FOR_avx2_pbroadcastv32qi_1 = 2767, CODE_FOR_avx2_pbroadcastv16hi_1 = 2768, CODE_FOR_avx2_pbroadcastv8si_1 = 2769, CODE_FOR_avx2_pbroadcastv4di_1 = 2770, CODE_FOR_avx2_permvarv8si = 2771, #define CODE_FOR_avx2_permvarv8si_mask CODE_FOR_nothing CODE_FOR_avx2_permvarv8sf = 2772, #define CODE_FOR_avx2_permvarv8sf_mask CODE_FOR_nothing CODE_FOR_avx512f_permvarv16si = 2773, CODE_FOR_avx512f_permvarv16si_mask = 2774, CODE_FOR_avx512f_permvarv16sf = 2775, CODE_FOR_avx512f_permvarv16sf_mask = 2776, CODE_FOR_avx512f_permvarv8di = 2777, CODE_FOR_avx512f_permvarv8di_mask = 2778, CODE_FOR_avx512f_permvarv8df = 2779, CODE_FOR_avx512f_permvarv8df_mask = 2780, CODE_FOR_avx2_permv4di_1 = 2781, #define CODE_FOR_avx2_permv4di_1_mask CODE_FOR_nothing CODE_FOR_avx2_permv4df_1 = 2782, #define CODE_FOR_avx2_permv4df_1_mask CODE_FOR_nothing CODE_FOR_avx512f_permv8di_1 = 2783, CODE_FOR_avx512f_permv8di_1_mask = 2784, CODE_FOR_avx512f_permv8df_1 = 2785, CODE_FOR_avx512f_permv8df_1_mask = 2786, CODE_FOR_avx2_permv2ti = 2787, CODE_FOR_avx2_vec_dupv4df = 2788, CODE_FOR_vec_dupv8si = 2789, CODE_FOR_vec_dupv8sf = 2790, CODE_FOR_vec_dupv4di = 2791, CODE_FOR_vec_dupv4df = 2792, CODE_FOR_avx512f_vec_dupv16si_mask = 2794, CODE_FOR_avx512f_vec_dupv16sf_mask = 2796, CODE_FOR_avx512f_vec_dupv8di_mask = 2798, CODE_FOR_avx512f_vec_dupv8df_mask = 2800, CODE_FOR_avx512f_broadcastv16sf_mask = 2802, CODE_FOR_avx512f_broadcastv16si_mask = 2804, CODE_FOR_avx512f_broadcastv8df_mask = 2806, CODE_FOR_avx512f_broadcastv8di_mask = 2808, CODE_FOR_avx512f_vec_dup_gprv16si_mask = 2810, CODE_FOR_avx512f_vec_dup_gprv8di_mask = 2812, CODE_FOR_avx512f_vec_dup_memv16si_mask = 2814, CODE_FOR_avx512f_vec_dup_memv16sf_mask = 2816, CODE_FOR_avx512f_vec_dup_memv8di_mask = 2818, CODE_FOR_avx512f_vec_dup_memv8df_mask = 2820, CODE_FOR_avx2_vbroadcasti128_v32qi = 2821, CODE_FOR_avx2_vbroadcasti128_v16hi = 2822, CODE_FOR_avx2_vbroadcasti128_v8si = 2823, CODE_FOR_avx2_vbroadcasti128_v4di = 2824, CODE_FOR_avx_vbroadcastf128_v32qi = 2825, CODE_FOR_avx_vbroadcastf128_v16hi = 2826, CODE_FOR_avx_vbroadcastf128_v8si = 2827, CODE_FOR_avx_vbroadcastf128_v4di = 2828, CODE_FOR_avx_vbroadcastf128_v8sf = 2829, CODE_FOR_avx_vbroadcastf128_v4df = 2830, CODE_FOR_avx512cd_maskb_vec_dupv8di = 2831, CODE_FOR_avx512cd_maskw_vec_dupv16si = 2832, CODE_FOR_avx512f_vpermilvarv16sf3 = 2844, CODE_FOR_avx512f_vpermilvarv16sf3_mask = 2845, CODE_FOR_avx_vpermilvarv8sf3 = 2846, #define CODE_FOR_avx_vpermilvarv8sf3_mask CODE_FOR_nothing CODE_FOR_avx_vpermilvarv4sf3 = 2847, #define CODE_FOR_avx_vpermilvarv4sf3_mask CODE_FOR_nothing CODE_FOR_avx512f_vpermilvarv8df3 = 2848, CODE_FOR_avx512f_vpermilvarv8df3_mask = 2849, CODE_FOR_avx_vpermilvarv4df3 = 2850, #define CODE_FOR_avx_vpermilvarv4df3_mask CODE_FOR_nothing CODE_FOR_avx_vpermilvarv2df3 = 2851, #define CODE_FOR_avx_vpermilvarv2df3_mask CODE_FOR_nothing CODE_FOR_avx512f_vpermi2varv16si3 = 2852, CODE_FOR_avx512f_vpermi2varv16si3_maskz_1 = 2853, CODE_FOR_avx512f_vpermi2varv16sf3 = 2854, CODE_FOR_avx512f_vpermi2varv16sf3_maskz_1 = 2855, CODE_FOR_avx512f_vpermi2varv8di3 = 2856, CODE_FOR_avx512f_vpermi2varv8di3_maskz_1 = 2857, CODE_FOR_avx512f_vpermi2varv8df3 = 2858, CODE_FOR_avx512f_vpermi2varv8df3_maskz_1 = 2859, CODE_FOR_avx512f_vpermi2varv16si3_mask = 2860, CODE_FOR_avx512f_vpermi2varv16sf3_mask = 2861, CODE_FOR_avx512f_vpermi2varv8di3_mask = 2862, CODE_FOR_avx512f_vpermi2varv8df3_mask = 2863, CODE_FOR_avx512f_vpermt2varv16si3 = 2864, CODE_FOR_avx512f_vpermt2varv16si3_maskz_1 = 2865, CODE_FOR_avx512f_vpermt2varv16sf3 = 2866, CODE_FOR_avx512f_vpermt2varv16sf3_maskz_1 = 2867, CODE_FOR_avx512f_vpermt2varv8di3 = 2868, CODE_FOR_avx512f_vpermt2varv8di3_maskz_1 = 2869, CODE_FOR_avx512f_vpermt2varv8df3 = 2870, CODE_FOR_avx512f_vpermt2varv8df3_maskz_1 = 2871, CODE_FOR_avx512f_vpermt2varv16si3_mask = 2872, CODE_FOR_avx512f_vpermt2varv16sf3_mask = 2873, CODE_FOR_avx512f_vpermt2varv8di3_mask = 2874, CODE_FOR_avx512f_vpermt2varv8df3_mask = 2875, CODE_FOR_avx2_vec_set_lo_v4di = 2882, CODE_FOR_avx2_vec_set_hi_v4di = 2883, CODE_FOR_vec_set_lo_v4di = 2884, CODE_FOR_vec_set_lo_v4df = 2885, CODE_FOR_vec_set_hi_v4di = 2886, CODE_FOR_vec_set_hi_v4df = 2887, CODE_FOR_vec_set_lo_v8si = 2888, CODE_FOR_vec_set_lo_v8sf = 2889, CODE_FOR_vec_set_hi_v8si = 2890, CODE_FOR_vec_set_hi_v8sf = 2891, CODE_FOR_vec_set_lo_v16hi = 2892, CODE_FOR_vec_set_hi_v16hi = 2893, CODE_FOR_vec_set_lo_v32qi = 2894, CODE_FOR_vec_set_hi_v32qi = 2895, CODE_FOR_avx_maskloadps = 2896, CODE_FOR_avx_maskloadpd = 2897, CODE_FOR_avx_maskloadps256 = 2898, CODE_FOR_avx_maskloadpd256 = 2899, CODE_FOR_avx2_maskloadd = 2900, CODE_FOR_avx2_maskloadq = 2901, CODE_FOR_avx2_maskloadd256 = 2902, CODE_FOR_avx2_maskloadq256 = 2903, CODE_FOR_avx_maskstoreps = 2904, CODE_FOR_avx_maskstorepd = 2905, CODE_FOR_avx_maskstoreps256 = 2906, CODE_FOR_avx_maskstorepd256 = 2907, CODE_FOR_avx2_maskstored = 2908, CODE_FOR_avx2_maskstoreq = 2909, CODE_FOR_avx2_maskstored256 = 2910, CODE_FOR_avx2_maskstoreq256 = 2911, CODE_FOR_avx_si256_si = 2912, CODE_FOR_avx_ps256_ps = 2913, CODE_FOR_avx_pd256_pd = 2914, CODE_FOR_avx512f_ashrvv16si = 2915, CODE_FOR_avx512f_ashrvv16si_mask = 2916, CODE_FOR_avx2_ashrvv8si = 2917, #define CODE_FOR_avx2_ashrvv8si_mask CODE_FOR_nothing CODE_FOR_avx2_ashrvv4si = 2918, #define CODE_FOR_avx2_ashrvv4si_mask CODE_FOR_nothing CODE_FOR_avx512f_ashrvv8di = 2919, CODE_FOR_avx512f_ashrvv8di_mask = 2920, CODE_FOR_avx512f_ashlvv16si = 2921, CODE_FOR_avx512f_ashlvv16si_mask = 2922, CODE_FOR_avx512f_lshrvv16si = 2923, CODE_FOR_avx512f_lshrvv16si_mask = 2924, CODE_FOR_avx2_ashlvv8si = 2925, #define CODE_FOR_avx2_ashlvv8si_mask CODE_FOR_nothing CODE_FOR_avx2_lshrvv8si = 2926, #define CODE_FOR_avx2_lshrvv8si_mask CODE_FOR_nothing CODE_FOR_avx2_ashlvv4si = 2927, #define CODE_FOR_avx2_ashlvv4si_mask CODE_FOR_nothing CODE_FOR_avx2_lshrvv4si = 2928, #define CODE_FOR_avx2_lshrvv4si_mask CODE_FOR_nothing CODE_FOR_avx512f_ashlvv8di = 2929, CODE_FOR_avx512f_ashlvv8di_mask = 2930, CODE_FOR_avx512f_lshrvv8di = 2931, CODE_FOR_avx512f_lshrvv8di_mask = 2932, CODE_FOR_avx2_ashlvv4di = 2933, #define CODE_FOR_avx2_ashlvv4di_mask CODE_FOR_nothing CODE_FOR_avx2_lshrvv4di = 2934, #define CODE_FOR_avx2_lshrvv4di_mask CODE_FOR_nothing CODE_FOR_avx2_ashlvv2di = 2935, #define CODE_FOR_avx2_ashlvv2di_mask CODE_FOR_nothing CODE_FOR_avx2_lshrvv2di = 2936, #define CODE_FOR_avx2_lshrvv2di_mask CODE_FOR_nothing CODE_FOR_avx_vec_concatv32qi = 2937, CODE_FOR_avx_vec_concatv16hi = 2938, CODE_FOR_avx_vec_concatv8si = 2939, CODE_FOR_avx_vec_concatv4di = 2940, CODE_FOR_avx_vec_concatv8sf = 2941, CODE_FOR_avx_vec_concatv4df = 2942, CODE_FOR_avx_vec_concatv64qi = 2943, CODE_FOR_avx_vec_concatv32hi = 2944, CODE_FOR_avx_vec_concatv16si = 2945, CODE_FOR_avx_vec_concatv8di = 2946, CODE_FOR_avx_vec_concatv16sf = 2947, CODE_FOR_avx_vec_concatv8df = 2948, CODE_FOR_vcvtph2ps = 2949, CODE_FOR_vcvtph2ps256 = 2951, CODE_FOR_avx512f_vcvtph2ps512_mask = 2954, CODE_FOR_avx512f_vcvtph2ps512_mask_round = 2955, CODE_FOR_vcvtps2ph256 = 2958, CODE_FOR_avx512f_vcvtps2ph512_mask = 2960, CODE_FOR_avx512f_compressv16si_mask = 3081, CODE_FOR_avx512f_compressv16sf_mask = 3082, CODE_FOR_avx512f_compressv8di_mask = 3083, CODE_FOR_avx512f_compressv8df_mask = 3084, CODE_FOR_avx512f_compressstorev16si_mask = 3085, CODE_FOR_avx512f_compressstorev16sf_mask = 3086, CODE_FOR_avx512f_compressstorev8di_mask = 3087, CODE_FOR_avx512f_compressstorev8df_mask = 3088, CODE_FOR_avx512f_expandv16si_mask = 3089, CODE_FOR_avx512f_expandv16sf_mask = 3090, CODE_FOR_avx512f_expandv8di_mask = 3091, CODE_FOR_avx512f_expandv8df_mask = 3092, CODE_FOR_avx512f_getmantv16sf = 3093, CODE_FOR_avx512f_getmantv16sf_round = 3094, CODE_FOR_avx512f_getmantv16sf_mask = 3095, CODE_FOR_avx512f_getmantv16sf_mask_round = 3096, CODE_FOR_avx512f_getmantv8df = 3097, CODE_FOR_avx512f_getmantv8df_round = 3098, CODE_FOR_avx512f_getmantv8df_mask = 3099, CODE_FOR_avx512f_getmantv8df_mask_round = 3100, CODE_FOR_avx512f_getmantv4sf = 3101, CODE_FOR_avx512f_getmantv4sf_round = 3102, CODE_FOR_avx512f_getmantv2df = 3103, CODE_FOR_avx512f_getmantv2df_round = 3104, CODE_FOR_clzv16si2 = 3105, CODE_FOR_clzv16si2_mask = 3106, CODE_FOR_clzv8di2 = 3107, CODE_FOR_clzv8di2_mask = 3108, CODE_FOR_conflictv16si_mask = 3110, CODE_FOR_conflictv8di_mask = 3112, CODE_FOR_sha1msg1 = 3113, CODE_FOR_sha1msg2 = 3114, CODE_FOR_sha1nexte = 3115, CODE_FOR_sha1rnds4 = 3116, CODE_FOR_sha256msg1 = 3117, CODE_FOR_sha256msg2 = 3118, CODE_FOR_sha256rnds2 = 3119, CODE_FOR_mfence_sse2 = 3122, CODE_FOR_mfence_nosse = 3123, CODE_FOR_atomic_loaddi_fpu = 3124, CODE_FOR_atomic_storeqi_1 = 3125, CODE_FOR_atomic_storehi_1 = 3126, CODE_FOR_atomic_storesi_1 = 3127, CODE_FOR_atomic_storedi_1 = 3128, CODE_FOR_atomic_storedi_fpu = 3129, CODE_FOR_loaddi_via_fpu = 3130, CODE_FOR_storedi_via_fpu = 3131, CODE_FOR_atomic_compare_and_swapqi_1 = 3132, CODE_FOR_atomic_compare_and_swaphi_1 = 3133, CODE_FOR_atomic_compare_and_swapsi_1 = 3134, CODE_FOR_atomic_compare_and_swapdi_1 = 3135, CODE_FOR_atomic_compare_and_swapdi_doubleword = 3136, CODE_FOR_atomic_compare_and_swapti_doubleword = 3137, CODE_FOR_atomic_fetch_addqi = 3138, CODE_FOR_atomic_fetch_addhi = 3139, CODE_FOR_atomic_fetch_addsi = 3140, CODE_FOR_atomic_fetch_adddi = 3141, CODE_FOR_atomic_exchangeqi = 3146, CODE_FOR_atomic_exchangehi = 3147, CODE_FOR_atomic_exchangesi = 3148, CODE_FOR_atomic_exchangedi = 3149, CODE_FOR_atomic_addqi = 3150, CODE_FOR_atomic_addhi = 3151, CODE_FOR_atomic_addsi = 3152, CODE_FOR_atomic_adddi = 3153, CODE_FOR_atomic_subqi = 3154, CODE_FOR_atomic_subhi = 3155, CODE_FOR_atomic_subsi = 3156, CODE_FOR_atomic_subdi = 3157, CODE_FOR_atomic_andqi = 3158, CODE_FOR_atomic_orqi = 3159, CODE_FOR_atomic_xorqi = 3160, CODE_FOR_atomic_andhi = 3161, CODE_FOR_atomic_orhi = 3162, CODE_FOR_atomic_xorhi = 3163, CODE_FOR_atomic_andsi = 3164, CODE_FOR_atomic_orsi = 3165, CODE_FOR_atomic_xorsi = 3166, CODE_FOR_atomic_anddi = 3167, CODE_FOR_atomic_ordi = 3168, CODE_FOR_atomic_xordi = 3169, CODE_FOR_cbranchqi4 = 3170, CODE_FOR_cbranchhi4 = 3171, CODE_FOR_cbranchsi4 = 3172, CODE_FOR_cbranchdi4 = 3173, CODE_FOR_cbranchti4 = 3174, CODE_FOR_cstoreqi4 = 3175, CODE_FOR_cstorehi4 = 3176, CODE_FOR_cstoresi4 = 3177, CODE_FOR_cstoredi4 = 3178, CODE_FOR_cmpsi_1 = 3179, CODE_FOR_cmpdi_1 = 3180, CODE_FOR_cmpqi_ext_3 = 3181, CODE_FOR_cbranchxf4 = 3182, CODE_FOR_cstorexf4 = 3183, CODE_FOR_cbranchsf4 = 3184, CODE_FOR_cbranchdf4 = 3185, CODE_FOR_cstoresf4 = 3186, CODE_FOR_cstoredf4 = 3187, CODE_FOR_cbranchcc4 = 3188, CODE_FOR_cstorecc4 = 3189, CODE_FOR_movxi = 3210, CODE_FOR_reload_noff_store = 3211, CODE_FOR_reload_noff_load = 3212, CODE_FOR_movoi = 3213, CODE_FOR_movti = 3214, CODE_FOR_movcdi = 3215, CODE_FOR_movqi = 3216, CODE_FOR_movhi = 3217, CODE_FOR_movsi = 3218, CODE_FOR_movdi = 3219, CODE_FOR_movstrictqi = 3222, CODE_FOR_movstricthi = 3223, CODE_FOR_movtf = 3234, CODE_FOR_movsf = 3235, CODE_FOR_movdf = 3236, CODE_FOR_movxf = 3237, CODE_FOR_zero_extendsidi2 = 3244, CODE_FOR_zero_extendqisi2 = 3248, CODE_FOR_zero_extendhisi2 = 3249, CODE_FOR_zero_extendqihi2 = 3252, CODE_FOR_extendsidi2 = 3254, CODE_FOR_extendsfdf2 = 3265, CODE_FOR_extendsfxf2 = 3268, CODE_FOR_extenddfxf2 = 3269, CODE_FOR_truncdfsf2 = 3270, CODE_FOR_truncdfsf2_with_temp = 3273, CODE_FOR_truncxfsf2 = 3275, CODE_FOR_truncxfdf2 = 3276, CODE_FOR_fix_truncxfdi2 = 3281, CODE_FOR_fix_truncsfdi2 = 3282, CODE_FOR_fix_truncdfdi2 = 3283, CODE_FOR_fix_truncxfsi2 = 3284, CODE_FOR_fix_truncsfsi2 = 3285, CODE_FOR_fix_truncdfsi2 = 3286, CODE_FOR_fix_truncsfhi2 = 3287, CODE_FOR_fix_truncdfhi2 = 3288, CODE_FOR_fix_truncxfhi2 = 3289, CODE_FOR_fixuns_truncsfsi2 = 3290, CODE_FOR_fixuns_truncdfsi2 = 3291, CODE_FOR_fixuns_truncsfhi2 = 3294, CODE_FOR_fixuns_truncdfhi2 = 3295, CODE_FOR_floatsisf2 = 3318, CODE_FOR_floatdisf2 = 3319, CODE_FOR_floatsidf2 = 3320, CODE_FOR_floatdidf2 = 3321, CODE_FOR_floatunsqisf2 = 3336, CODE_FOR_floatunshisf2 = 3337, CODE_FOR_floatunsqidf2 = 3338, CODE_FOR_floatunshidf2 = 3339, CODE_FOR_floatunssisf2 = 3343, CODE_FOR_floatunssidf2 = 3344, CODE_FOR_floatunssixf2 = 3345, CODE_FOR_floatunsdisf2 = 3346, CODE_FOR_floatunsdidf2 = 3347, CODE_FOR_addqi3 = 3350, CODE_FOR_addhi3 = 3351, CODE_FOR_addsi3 = 3352, CODE_FOR_adddi3 = 3353, CODE_FOR_addti3 = 3354, CODE_FOR_addvqi4 = 3365, CODE_FOR_addvhi4 = 3366, CODE_FOR_addvsi4 = 3367, CODE_FOR_addvdi4 = 3368, CODE_FOR_subqi3 = 3374, CODE_FOR_subhi3 = 3375, CODE_FOR_subsi3 = 3376, CODE_FOR_subdi3 = 3377, CODE_FOR_subti3 = 3378, CODE_FOR_subvqi4 = 3381, CODE_FOR_subvhi4 = 3382, CODE_FOR_subvsi4 = 3383, CODE_FOR_subvdi4 = 3384, CODE_FOR_addqi3_carry = 3385, CODE_FOR_subqi3_carry = 3386, CODE_FOR_addhi3_carry = 3387, CODE_FOR_subhi3_carry = 3388, CODE_FOR_addsi3_carry = 3389, CODE_FOR_subsi3_carry = 3390, CODE_FOR_adddi3_carry = 3391, CODE_FOR_subdi3_carry = 3392, CODE_FOR_addxf3 = 3393, CODE_FOR_subxf3 = 3394, CODE_FOR_addsf3 = 3395, CODE_FOR_subsf3 = 3396, CODE_FOR_adddf3 = 3397, CODE_FOR_subdf3 = 3398, CODE_FOR_mulhi3 = 3399, CODE_FOR_mulsi3 = 3400, CODE_FOR_muldi3 = 3401, CODE_FOR_mulqi3 = 3402, CODE_FOR_mulvsi4 = 3403, CODE_FOR_mulvdi4 = 3404, CODE_FOR_mulsidi3 = 3405, CODE_FOR_umulsidi3 = 3406, CODE_FOR_mulditi3 = 3407, CODE_FOR_umulditi3 = 3408, CODE_FOR_mulqihi3 = 3409, CODE_FOR_umulqihi3 = 3410, CODE_FOR_smulsi3_highpart = 3413, CODE_FOR_umulsi3_highpart = 3414, CODE_FOR_smuldi3_highpart = 3415, CODE_FOR_umuldi3_highpart = 3416, CODE_FOR_mulxf3 = 3417, CODE_FOR_mulsf3 = 3418, CODE_FOR_muldf3 = 3419, CODE_FOR_divxf3 = 3420, CODE_FOR_divdf3 = 3421, CODE_FOR_divsf3 = 3422, CODE_FOR_divmodhi4 = 3423, CODE_FOR_divmodsi4 = 3424, CODE_FOR_divmoddi4 = 3425, CODE_FOR_divmodqi4 = 3433, CODE_FOR_udivmodhi4 = 3434, CODE_FOR_udivmodsi4 = 3435, CODE_FOR_udivmoddi4 = 3436, CODE_FOR_udivmodqi4 = 3444, CODE_FOR_testsi_ccno_1 = 3445, CODE_FOR_testqi_ccz_1 = 3446, CODE_FOR_testdi_ccno_1 = 3447, CODE_FOR_testqi_ext_ccno_0 = 3448, CODE_FOR_andqi3 = 3458, CODE_FOR_andhi3 = 3459, CODE_FOR_andsi3 = 3460, CODE_FOR_anddi3 = 3461, CODE_FOR_iorqi3 = 3473, CODE_FOR_xorqi3 = 3474, CODE_FOR_iorhi3 = 3475, CODE_FOR_xorhi3 = 3476, CODE_FOR_iorsi3 = 3477, CODE_FOR_xorsi3 = 3478, CODE_FOR_iordi3 = 3479, CODE_FOR_xordi3 = 3480, CODE_FOR_xorqi_cc_ext_1 = 3487, CODE_FOR_negqi2 = 3488, CODE_FOR_neghi2 = 3489, CODE_FOR_negsi2 = 3490, CODE_FOR_negdi2 = 3491, CODE_FOR_negti2 = 3492, CODE_FOR_negvqi3 = 3495, CODE_FOR_negvhi3 = 3496, CODE_FOR_negvsi3 = 3497, CODE_FOR_negvdi3 = 3498, CODE_FOR_abssf2 = 3499, CODE_FOR_negsf2 = 3500, CODE_FOR_absdf2 = 3501, CODE_FOR_negdf2 = 3502, CODE_FOR_absxf2 = 3503, CODE_FOR_negxf2 = 3504, CODE_FOR_abstf2 = 3505, CODE_FOR_negtf2 = 3506, CODE_FOR_copysignsf3 = 3512, CODE_FOR_copysigndf3 = 3513, CODE_FOR_copysigntf3 = 3514, CODE_FOR_one_cmplqi2 = 3521, CODE_FOR_one_cmplhi2 = 3522, CODE_FOR_one_cmplsi2 = 3523, CODE_FOR_one_cmpldi2 = 3524, CODE_FOR_ashlqi3 = 3530, CODE_FOR_ashlhi3 = 3531, CODE_FOR_ashlsi3 = 3532, CODE_FOR_ashldi3 = 3533, CODE_FOR_ashlti3 = 3534, CODE_FOR_x86_shiftsi_adj_1 = 3539, CODE_FOR_x86_shiftdi_adj_1 = 3540, CODE_FOR_x86_shiftsi_adj_2 = 3541, CODE_FOR_x86_shiftdi_adj_2 = 3542, CODE_FOR_lshrqi3 = 3548, CODE_FOR_ashrqi3 = 3549, CODE_FOR_lshrhi3 = 3550, CODE_FOR_ashrhi3 = 3551, CODE_FOR_lshrsi3 = 3552, CODE_FOR_ashrsi3 = 3553, CODE_FOR_lshrdi3 = 3554, CODE_FOR_ashrdi3 = 3555, CODE_FOR_lshrti3 = 3556, CODE_FOR_ashrti3 = 3557, CODE_FOR_x86_shiftsi_adj_3 = 3566, CODE_FOR_x86_shiftdi_adj_3 = 3567, CODE_FOR_rotlti3 = 3574, CODE_FOR_rotrti3 = 3575, CODE_FOR_rotldi3 = 3576, CODE_FOR_rotrdi3 = 3577, CODE_FOR_rotlqi3 = 3578, CODE_FOR_rotrqi3 = 3579, CODE_FOR_rotlhi3 = 3580, CODE_FOR_rotrhi3 = 3581, CODE_FOR_rotlsi3 = 3582, CODE_FOR_rotrsi3 = 3583, CODE_FOR_extv = 3596, CODE_FOR_extzv = 3597, CODE_FOR_insv = 3598, CODE_FOR_indirect_jump = 3631, CODE_FOR_tablejump = 3632, CODE_FOR_call = 3637, CODE_FOR_sibcall = 3638, CODE_FOR_call_pop = 3639, CODE_FOR_call_value = 3640, CODE_FOR_sibcall_value = 3641, CODE_FOR_call_value_pop = 3642, CODE_FOR_untyped_call = 3643, CODE_FOR_memory_blockage = 3644, CODE_FOR_return = 3645, CODE_FOR_simple_return = 3646, CODE_FOR_prologue = 3647, CODE_FOR_epilogue = 3648, CODE_FOR_sibcall_epilogue = 3649, CODE_FOR_eh_return = 3650, CODE_FOR_split_stack_prologue = 3652, CODE_FOR_split_stack_space_check = 3653, CODE_FOR_ffssi2 = 3654, CODE_FOR_ffsdi2 = 3655, CODE_FOR_ctzhi2 = 3657, CODE_FOR_ctzsi2 = 3658, CODE_FOR_ctzdi2 = 3659, CODE_FOR_clzhi2 = 3662, CODE_FOR_clzsi2 = 3663, CODE_FOR_clzdi2 = 3664, CODE_FOR_clzhi2_lzcnt = 3665, CODE_FOR_clzsi2_lzcnt = 3666, CODE_FOR_clzdi2_lzcnt = 3667, CODE_FOR_bmi2_bzhi_si3 = 3670, CODE_FOR_bmi2_bzhi_di3 = 3671, CODE_FOR_popcounthi2 = 3672, CODE_FOR_popcountsi2 = 3673, CODE_FOR_popcountdi2 = 3674, CODE_FOR_bswapdi2 = 3677, CODE_FOR_bswapsi2 = 3678, CODE_FOR_paritydi2 = 3679, CODE_FOR_paritysi2 = 3680, CODE_FOR_tls_global_dynamic_32 = 3683, CODE_FOR_tls_global_dynamic_64_si = 3684, CODE_FOR_tls_global_dynamic_64_di = 3685, CODE_FOR_tls_local_dynamic_base_32 = 3686, CODE_FOR_tls_local_dynamic_base_64_si = 3687, CODE_FOR_tls_local_dynamic_base_64_di = 3688, CODE_FOR_tls_dynamic_gnu2_32 = 3690, CODE_FOR_tls_dynamic_gnu2_64 = 3692, CODE_FOR_rsqrtsf2 = 3694, CODE_FOR_sqrtsf2 = 3695, CODE_FOR_sqrtdf2 = 3696, CODE_FOR_fmodxf3 = 3697, CODE_FOR_fmodsf3 = 3698, CODE_FOR_fmoddf3 = 3699, CODE_FOR_remainderxf3 = 3700, CODE_FOR_remaindersf3 = 3701, CODE_FOR_remainderdf3 = 3702, CODE_FOR_sincossf3 = 3709, CODE_FOR_sincosdf3 = 3710, CODE_FOR_tanxf2 = 3711, CODE_FOR_tansf2 = 3712, CODE_FOR_tandf2 = 3713, CODE_FOR_atan2xf3 = 3714, CODE_FOR_atan2sf3 = 3715, CODE_FOR_atan2df3 = 3716, CODE_FOR_atanxf2 = 3717, CODE_FOR_atansf2 = 3718, CODE_FOR_atandf2 = 3719, CODE_FOR_asinxf2 = 3720, CODE_FOR_asinsf2 = 3721, CODE_FOR_asindf2 = 3722, CODE_FOR_acosxf2 = 3723, CODE_FOR_acossf2 = 3724, CODE_FOR_acosdf2 = 3725, CODE_FOR_logxf2 = 3726, CODE_FOR_logsf2 = 3727, CODE_FOR_logdf2 = 3728, CODE_FOR_log10xf2 = 3729, CODE_FOR_log10sf2 = 3730, CODE_FOR_log10df2 = 3731, CODE_FOR_log2xf2 = 3732, CODE_FOR_log2sf2 = 3733, CODE_FOR_log2df2 = 3734, CODE_FOR_log1pxf2 = 3735, CODE_FOR_log1psf2 = 3736, CODE_FOR_log1pdf2 = 3737, CODE_FOR_logbxf2 = 3738, CODE_FOR_logbsf2 = 3739, CODE_FOR_logbdf2 = 3740, CODE_FOR_ilogbxf2 = 3741, CODE_FOR_ilogbsf2 = 3742, CODE_FOR_ilogbdf2 = 3743, CODE_FOR_expNcorexf3 = 3744, CODE_FOR_expxf2 = 3745, CODE_FOR_expsf2 = 3746, CODE_FOR_expdf2 = 3747, CODE_FOR_exp10xf2 = 3748, CODE_FOR_exp10sf2 = 3749, CODE_FOR_exp10df2 = 3750, CODE_FOR_exp2xf2 = 3751, CODE_FOR_exp2sf2 = 3752, CODE_FOR_exp2df2 = 3753, CODE_FOR_expm1xf2 = 3754, CODE_FOR_expm1sf2 = 3755, CODE_FOR_expm1df2 = 3756, CODE_FOR_ldexpxf3 = 3757, CODE_FOR_ldexpsf3 = 3758, CODE_FOR_ldexpdf3 = 3759, CODE_FOR_scalbxf3 = 3760, CODE_FOR_scalbsf3 = 3761, CODE_FOR_scalbdf3 = 3762, CODE_FOR_significandxf2 = 3763, CODE_FOR_significandsf2 = 3764, CODE_FOR_significanddf2 = 3765, CODE_FOR_rintsf2 = 3766, CODE_FOR_rintdf2 = 3767, CODE_FOR_roundsf2 = 3768, CODE_FOR_rounddf2 = 3769, CODE_FOR_roundxf2 = 3770, CODE_FOR_lrintxfhi2 = 3780, CODE_FOR_lrintxfsi2 = 3781, CODE_FOR_lrintxfdi2 = 3782, CODE_FOR_lrintsfsi2 = 3783, CODE_FOR_lrintsfdi2 = 3784, CODE_FOR_lrintdfsi2 = 3785, CODE_FOR_lrintdfdi2 = 3786, CODE_FOR_lroundsfhi2 = 3787, CODE_FOR_lrounddfhi2 = 3788, CODE_FOR_lroundxfhi2 = 3789, CODE_FOR_lroundsfsi2 = 3790, CODE_FOR_lrounddfsi2 = 3791, CODE_FOR_lroundxfsi2 = 3792, CODE_FOR_lroundsfdi2 = 3793, CODE_FOR_lrounddfdi2 = 3794, CODE_FOR_lroundxfdi2 = 3795, CODE_FOR_floorxf2 = 3799, CODE_FOR_ceilxf2 = 3800, CODE_FOR_btruncxf2 = 3801, CODE_FOR_floorsf2 = 3802, CODE_FOR_ceilsf2 = 3803, CODE_FOR_btruncsf2 = 3804, CODE_FOR_floordf2 = 3805, CODE_FOR_ceildf2 = 3806, CODE_FOR_btruncdf2 = 3807, CODE_FOR_nearbyintxf2 = 3809, CODE_FOR_nearbyintsf2 = 3810, CODE_FOR_nearbyintdf2 = 3811, CODE_FOR_lfloorxfhi2 = 3830, CODE_FOR_lceilxfhi2 = 3831, CODE_FOR_lfloorxfsi2 = 3832, CODE_FOR_lceilxfsi2 = 3833, CODE_FOR_lfloorxfdi2 = 3834, CODE_FOR_lceilxfdi2 = 3835, CODE_FOR_lfloorsfsi2 = 3836, CODE_FOR_lceilsfsi2 = 3837, CODE_FOR_lfloorsfdi2 = 3838, CODE_FOR_lceilsfdi2 = 3839, CODE_FOR_lfloordfsi2 = 3840, CODE_FOR_lceildfsi2 = 3841, CODE_FOR_lfloordfdi2 = 3842, CODE_FOR_lceildfdi2 = 3843, CODE_FOR_isinfxf2 = 3846, CODE_FOR_isinfsf2 = 3847, CODE_FOR_isinfdf2 = 3848, CODE_FOR_signbitxf2 = 3849, CODE_FOR_signbitdf2 = 3850, CODE_FOR_signbitsf2 = 3851, CODE_FOR_movmemsi = 3852, CODE_FOR_movmemdi = 3853, CODE_FOR_strmov = 3854, CODE_FOR_strmov_singleop = 3855, CODE_FOR_rep_mov = 3856, CODE_FOR_setmemsi = 3857, CODE_FOR_setmemdi = 3858, CODE_FOR_strset = 3859, CODE_FOR_strset_singleop = 3860, CODE_FOR_rep_stos = 3861, CODE_FOR_cmpstrnsi = 3862, CODE_FOR_cmpintqi = 3863, CODE_FOR_cmpstrnqi_nz_1 = 3864, CODE_FOR_cmpstrnqi_1 = 3865, CODE_FOR_strlensi = 3866, CODE_FOR_strlendi = 3867, CODE_FOR_strlenqi_1 = 3868, CODE_FOR_movqicc = 3871, CODE_FOR_movhicc = 3872, CODE_FOR_movsicc = 3873, CODE_FOR_movdicc = 3874, CODE_FOR_x86_movsicc_0_m1 = 3875, CODE_FOR_x86_movdicc_0_m1 = 3876, CODE_FOR_movsfcc = 3888, CODE_FOR_movdfcc = 3889, CODE_FOR_movxfcc = 3890, CODE_FOR_addqicc = 3899, CODE_FOR_addhicc = 3900, CODE_FOR_addsicc = 3901, CODE_FOR_adddicc = 3902, CODE_FOR_allocate_stack = 3903, CODE_FOR_probe_stack = 3904, CODE_FOR_builtin_setjmp_receiver = 3905, CODE_FOR_prefetch = 4012, CODE_FOR_stack_protect_set = 4013, CODE_FOR_stack_protect_test = 4014, CODE_FOR_lwp_llwpcb = 4015, CODE_FOR_lwp_slwpcb = 4016, CODE_FOR_lwp_lwpvalsi3 = 4017, CODE_FOR_lwp_lwpvaldi3 = 4018, CODE_FOR_lwp_lwpinssi3 = 4019, CODE_FOR_lwp_lwpinsdi3 = 4020, CODE_FOR_pause = 4021, CODE_FOR_xbegin = 4022, CODE_FOR_xtest = 4023, CODE_FOR_movv8qi = 4024, CODE_FOR_movv4hi = 4025, CODE_FOR_movv2si = 4026, CODE_FOR_movv1di = 4027, CODE_FOR_movv2sf = 4028, CODE_FOR_movmisalignv8qi = 4034, CODE_FOR_movmisalignv4hi = 4035, CODE_FOR_movmisalignv2si = 4036, CODE_FOR_movmisalignv1di = 4037, CODE_FOR_movmisalignv2sf = 4038, CODE_FOR_mmx_addv2sf3 = 4039, CODE_FOR_mmx_subv2sf3 = 4040, CODE_FOR_mmx_subrv2sf3 = 4041, CODE_FOR_mmx_mulv2sf3 = 4042, CODE_FOR_mmx_smaxv2sf3 = 4043, CODE_FOR_mmx_sminv2sf3 = 4044, CODE_FOR_mmx_eqv2sf3 = 4045, CODE_FOR_vec_setv2sf = 4046, CODE_FOR_vec_extractv2sf = 4049, CODE_FOR_vec_initv2sf = 4050, CODE_FOR_mmx_addv8qi3 = 4051, CODE_FOR_mmx_subv8qi3 = 4052, CODE_FOR_mmx_addv4hi3 = 4053, CODE_FOR_mmx_subv4hi3 = 4054, CODE_FOR_mmx_addv2si3 = 4055, CODE_FOR_mmx_subv2si3 = 4056, CODE_FOR_mmx_addv1di3 = 4057, CODE_FOR_mmx_subv1di3 = 4058, CODE_FOR_mmx_ssaddv8qi3 = 4059, CODE_FOR_mmx_usaddv8qi3 = 4060, CODE_FOR_mmx_sssubv8qi3 = 4061, CODE_FOR_mmx_ussubv8qi3 = 4062, CODE_FOR_mmx_ssaddv4hi3 = 4063, CODE_FOR_mmx_usaddv4hi3 = 4064, CODE_FOR_mmx_sssubv4hi3 = 4065, CODE_FOR_mmx_ussubv4hi3 = 4066, CODE_FOR_mmx_mulv4hi3 = 4067, CODE_FOR_mmx_smulv4hi3_highpart = 4068, CODE_FOR_mmx_umulv4hi3_highpart = 4069, CODE_FOR_mmx_pmaddwd = 4070, CODE_FOR_mmx_pmulhrwv4hi3 = 4071, CODE_FOR_sse2_umulv1siv1di3 = 4072, CODE_FOR_mmx_smaxv4hi3 = 4073, CODE_FOR_mmx_sminv4hi3 = 4074, CODE_FOR_mmx_umaxv8qi3 = 4075, CODE_FOR_mmx_uminv8qi3 = 4076, CODE_FOR_mmx_eqv8qi3 = 4077, CODE_FOR_mmx_eqv4hi3 = 4078, CODE_FOR_mmx_eqv2si3 = 4079, CODE_FOR_mmx_andv8qi3 = 4080, CODE_FOR_mmx_iorv8qi3 = 4081, CODE_FOR_mmx_xorv8qi3 = 4082, CODE_FOR_mmx_andv4hi3 = 4083, CODE_FOR_mmx_iorv4hi3 = 4084, CODE_FOR_mmx_xorv4hi3 = 4085, CODE_FOR_mmx_andv2si3 = 4086, CODE_FOR_mmx_iorv2si3 = 4087, CODE_FOR_mmx_xorv2si3 = 4088, CODE_FOR_mmx_pinsrw = 4089, CODE_FOR_mmx_pshufw = 4090, CODE_FOR_vec_setv2si = 4091, CODE_FOR_vec_extractv2si = 4095, CODE_FOR_vec_initv2si = 4096, CODE_FOR_vec_setv4hi = 4097, CODE_FOR_vec_extractv4hi = 4098, CODE_FOR_vec_initv4hi = 4099, CODE_FOR_vec_setv8qi = 4100, CODE_FOR_vec_extractv8qi = 4101, CODE_FOR_vec_initv8qi = 4102, CODE_FOR_mmx_uavgv8qi3 = 4103, CODE_FOR_mmx_uavgv4hi3 = 4104, CODE_FOR_mmx_maskmovq = 4105, CODE_FOR_mmx_emms = 4106, CODE_FOR_mmx_femms = 4107, CODE_FOR_movv64qi = 4108, CODE_FOR_movv32qi = 4109, CODE_FOR_movv16qi = 4110, CODE_FOR_movv32hi = 4111, CODE_FOR_movv16hi = 4112, CODE_FOR_movv8hi = 4113, CODE_FOR_movv16si = 4114, CODE_FOR_movv8si = 4115, CODE_FOR_movv4si = 4116, CODE_FOR_movv8di = 4117, CODE_FOR_movv4di = 4118, CODE_FOR_movv2di = 4119, CODE_FOR_movv2ti = 4120, CODE_FOR_movv1ti = 4121, CODE_FOR_movv16sf = 4122, CODE_FOR_movv8sf = 4123, CODE_FOR_movv4sf = 4124, CODE_FOR_movv8df = 4125, CODE_FOR_movv4df = 4126, CODE_FOR_movv2df = 4127, CODE_FOR_movmisalignv64qi = 4131, CODE_FOR_movmisalignv32qi = 4132, CODE_FOR_movmisalignv16qi = 4133, CODE_FOR_movmisalignv32hi = 4134, CODE_FOR_movmisalignv16hi = 4135, CODE_FOR_movmisalignv8hi = 4136, CODE_FOR_movmisalignv16si = 4137, CODE_FOR_movmisalignv8si = 4138, CODE_FOR_movmisalignv4si = 4139, CODE_FOR_movmisalignv8di = 4140, CODE_FOR_movmisalignv4di = 4141, CODE_FOR_movmisalignv2di = 4142, CODE_FOR_movmisalignv2ti = 4143, CODE_FOR_movmisalignv1ti = 4144, CODE_FOR_movmisalignv16sf = 4145, CODE_FOR_movmisalignv8sf = 4146, CODE_FOR_movmisalignv4sf = 4147, CODE_FOR_movmisalignv8df = 4148, CODE_FOR_movmisalignv4df = 4149, CODE_FOR_movmisalignv2df = 4150, CODE_FOR_avx512f_loadups512 = 4151, CODE_FOR_avx512f_loadups512_mask = 4152, CODE_FOR_avx_loadups256 = 4153, #define CODE_FOR_avx_loadups256_mask CODE_FOR_nothing CODE_FOR_sse_loadups = 4154, #define CODE_FOR_sse_loadups_mask CODE_FOR_nothing CODE_FOR_avx512f_loadupd512 = 4155, CODE_FOR_avx512f_loadupd512_mask = 4156, CODE_FOR_avx_loadupd256 = 4157, #define CODE_FOR_avx_loadupd256_mask CODE_FOR_nothing CODE_FOR_sse2_loadupd = 4158, #define CODE_FOR_sse2_loadupd_mask CODE_FOR_nothing CODE_FOR_avx_loaddquv32qi = 4159, CODE_FOR_sse2_loaddquv16qi = 4160, #define CODE_FOR_sse2_loaddquv16qi_mask CODE_FOR_nothing CODE_FOR_avx512f_loaddquv16si = 4161, CODE_FOR_avx512f_loaddquv16si_mask = 4162, CODE_FOR_avx512f_loaddquv8di = 4163, CODE_FOR_avx512f_loaddquv8di_mask = 4164, CODE_FOR_storentdi = 4165, CODE_FOR_storentsi = 4166, CODE_FOR_storentsf = 4167, CODE_FOR_storentdf = 4168, CODE_FOR_storentv8di = 4169, CODE_FOR_storentv4di = 4170, CODE_FOR_storentv2di = 4171, CODE_FOR_storentv16sf = 4172, CODE_FOR_storentv8sf = 4173, CODE_FOR_storentv4sf = 4174, CODE_FOR_storentv8df = 4175, CODE_FOR_storentv4df = 4176, CODE_FOR_storentv2df = 4177, CODE_FOR_absv16sf2 = 4178, CODE_FOR_negv16sf2 = 4179, CODE_FOR_absv8sf2 = 4180, CODE_FOR_negv8sf2 = 4181, CODE_FOR_absv4sf2 = 4182, CODE_FOR_negv4sf2 = 4183, CODE_FOR_absv8df2 = 4184, CODE_FOR_negv8df2 = 4185, CODE_FOR_absv4df2 = 4186, CODE_FOR_negv4df2 = 4187, CODE_FOR_absv2df2 = 4188, CODE_FOR_negv2df2 = 4189, CODE_FOR_addv16sf3 = 4196, CODE_FOR_addv16sf3_round = 4197, CODE_FOR_addv16sf3_mask = 4198, CODE_FOR_addv16sf3_mask_round = 4199, CODE_FOR_subv16sf3 = 4200, CODE_FOR_subv16sf3_round = 4201, CODE_FOR_subv16sf3_mask = 4202, CODE_FOR_subv16sf3_mask_round = 4203, CODE_FOR_addv8sf3 = 4204, #define CODE_FOR_addv8sf3_round CODE_FOR_nothing #define CODE_FOR_addv8sf3_mask CODE_FOR_nothing #define CODE_FOR_addv8sf3_mask_round CODE_FOR_nothing CODE_FOR_subv8sf3 = 4205, #define CODE_FOR_subv8sf3_round CODE_FOR_nothing #define CODE_FOR_subv8sf3_mask CODE_FOR_nothing #define CODE_FOR_subv8sf3_mask_round CODE_FOR_nothing CODE_FOR_addv4sf3 = 4206, #define CODE_FOR_addv4sf3_round CODE_FOR_nothing #define CODE_FOR_addv4sf3_mask CODE_FOR_nothing #define CODE_FOR_addv4sf3_mask_round CODE_FOR_nothing CODE_FOR_subv4sf3 = 4207, #define CODE_FOR_subv4sf3_round CODE_FOR_nothing #define CODE_FOR_subv4sf3_mask CODE_FOR_nothing #define CODE_FOR_subv4sf3_mask_round CODE_FOR_nothing CODE_FOR_addv8df3 = 4208, CODE_FOR_addv8df3_round = 4209, CODE_FOR_addv8df3_mask = 4210, CODE_FOR_addv8df3_mask_round = 4211, CODE_FOR_subv8df3 = 4212, CODE_FOR_subv8df3_round = 4213, CODE_FOR_subv8df3_mask = 4214, CODE_FOR_subv8df3_mask_round = 4215, CODE_FOR_addv4df3 = 4216, #define CODE_FOR_addv4df3_round CODE_FOR_nothing #define CODE_FOR_addv4df3_mask CODE_FOR_nothing #define CODE_FOR_addv4df3_mask_round CODE_FOR_nothing CODE_FOR_subv4df3 = 4217, #define CODE_FOR_subv4df3_round CODE_FOR_nothing #define CODE_FOR_subv4df3_mask CODE_FOR_nothing #define CODE_FOR_subv4df3_mask_round CODE_FOR_nothing CODE_FOR_addv2df3 = 4218, #define CODE_FOR_addv2df3_round CODE_FOR_nothing #define CODE_FOR_addv2df3_mask CODE_FOR_nothing #define CODE_FOR_addv2df3_mask_round CODE_FOR_nothing CODE_FOR_subv2df3 = 4219, #define CODE_FOR_subv2df3_round CODE_FOR_nothing #define CODE_FOR_subv2df3_mask CODE_FOR_nothing #define CODE_FOR_subv2df3_mask_round CODE_FOR_nothing CODE_FOR_mulv16sf3 = 4220, CODE_FOR_mulv16sf3_round = 4221, CODE_FOR_mulv16sf3_mask = 4222, CODE_FOR_mulv16sf3_mask_round = 4223, CODE_FOR_mulv8sf3 = 4224, #define CODE_FOR_mulv8sf3_round CODE_FOR_nothing #define CODE_FOR_mulv8sf3_mask CODE_FOR_nothing #define CODE_FOR_mulv8sf3_mask_round CODE_FOR_nothing CODE_FOR_mulv4sf3 = 4225, #define CODE_FOR_mulv4sf3_round CODE_FOR_nothing #define CODE_FOR_mulv4sf3_mask CODE_FOR_nothing #define CODE_FOR_mulv4sf3_mask_round CODE_FOR_nothing CODE_FOR_mulv8df3 = 4226, CODE_FOR_mulv8df3_round = 4227, CODE_FOR_mulv8df3_mask = 4228, CODE_FOR_mulv8df3_mask_round = 4229, CODE_FOR_mulv4df3 = 4230, #define CODE_FOR_mulv4df3_round CODE_FOR_nothing #define CODE_FOR_mulv4df3_mask CODE_FOR_nothing #define CODE_FOR_mulv4df3_mask_round CODE_FOR_nothing CODE_FOR_mulv2df3 = 4231, #define CODE_FOR_mulv2df3_round CODE_FOR_nothing #define CODE_FOR_mulv2df3_mask CODE_FOR_nothing #define CODE_FOR_mulv2df3_mask_round CODE_FOR_nothing CODE_FOR_divv8df3 = 4232, CODE_FOR_divv4df3 = 4233, CODE_FOR_divv2df3 = 4234, CODE_FOR_divv16sf3 = 4235, CODE_FOR_divv8sf3 = 4236, CODE_FOR_divv4sf3 = 4237, CODE_FOR_sqrtv8df2 = 4238, CODE_FOR_sqrtv4df2 = 4239, CODE_FOR_sqrtv2df2 = 4240, CODE_FOR_sqrtv16sf2 = 4241, CODE_FOR_sqrtv8sf2 = 4242, CODE_FOR_sqrtv4sf2 = 4243, CODE_FOR_rsqrtv8sf2 = 4244, CODE_FOR_rsqrtv4sf2 = 4245, CODE_FOR_smaxv16sf3 = 4246, CODE_FOR_smaxv16sf3_round = 4247, CODE_FOR_smaxv16sf3_mask = 4248, CODE_FOR_smaxv16sf3_mask_round = 4249, CODE_FOR_sminv16sf3 = 4250, CODE_FOR_sminv16sf3_round = 4251, CODE_FOR_sminv16sf3_mask = 4252, CODE_FOR_sminv16sf3_mask_round = 4253, CODE_FOR_smaxv8sf3 = 4254, #define CODE_FOR_smaxv8sf3_round CODE_FOR_nothing #define CODE_FOR_smaxv8sf3_mask CODE_FOR_nothing #define CODE_FOR_smaxv8sf3_mask_round CODE_FOR_nothing CODE_FOR_sminv8sf3 = 4255, #define CODE_FOR_sminv8sf3_round CODE_FOR_nothing #define CODE_FOR_sminv8sf3_mask CODE_FOR_nothing #define CODE_FOR_sminv8sf3_mask_round CODE_FOR_nothing CODE_FOR_smaxv4sf3 = 4256, #define CODE_FOR_smaxv4sf3_round CODE_FOR_nothing #define CODE_FOR_smaxv4sf3_mask CODE_FOR_nothing #define CODE_FOR_smaxv4sf3_mask_round CODE_FOR_nothing CODE_FOR_sminv4sf3 = 4257, #define CODE_FOR_sminv4sf3_round CODE_FOR_nothing #define CODE_FOR_sminv4sf3_mask CODE_FOR_nothing #define CODE_FOR_sminv4sf3_mask_round CODE_FOR_nothing CODE_FOR_smaxv8df3 = 4258, CODE_FOR_smaxv8df3_round = 4259, CODE_FOR_smaxv8df3_mask = 4260, CODE_FOR_smaxv8df3_mask_round = 4261, CODE_FOR_sminv8df3 = 4262, CODE_FOR_sminv8df3_round = 4263, CODE_FOR_sminv8df3_mask = 4264, CODE_FOR_sminv8df3_mask_round = 4265, CODE_FOR_smaxv4df3 = 4266, #define CODE_FOR_smaxv4df3_round CODE_FOR_nothing #define CODE_FOR_smaxv4df3_mask CODE_FOR_nothing #define CODE_FOR_smaxv4df3_mask_round CODE_FOR_nothing CODE_FOR_sminv4df3 = 4267, #define CODE_FOR_sminv4df3_round CODE_FOR_nothing #define CODE_FOR_sminv4df3_mask CODE_FOR_nothing #define CODE_FOR_sminv4df3_mask_round CODE_FOR_nothing CODE_FOR_smaxv2df3 = 4268, #define CODE_FOR_smaxv2df3_round CODE_FOR_nothing #define CODE_FOR_smaxv2df3_mask CODE_FOR_nothing #define CODE_FOR_smaxv2df3_mask_round CODE_FOR_nothing CODE_FOR_sminv2df3 = 4269, #define CODE_FOR_sminv2df3_round CODE_FOR_nothing #define CODE_FOR_sminv2df3_mask CODE_FOR_nothing #define CODE_FOR_sminv2df3_mask_round CODE_FOR_nothing CODE_FOR_sse3_haddv2df3 = 4270, CODE_FOR_reduc_splus_v8df = 4271, CODE_FOR_reduc_splus_v4df = 4272, CODE_FOR_reduc_splus_v2df = 4273, CODE_FOR_reduc_splus_v16sf = 4274, CODE_FOR_reduc_splus_v8sf = 4275, CODE_FOR_reduc_splus_v4sf = 4276, CODE_FOR_reduc_smax_v32qi = 4277, CODE_FOR_reduc_smin_v32qi = 4278, CODE_FOR_reduc_smax_v16hi = 4279, CODE_FOR_reduc_smin_v16hi = 4280, CODE_FOR_reduc_smax_v8si = 4281, CODE_FOR_reduc_smin_v8si = 4282, CODE_FOR_reduc_smax_v4di = 4283, CODE_FOR_reduc_smin_v4di = 4284, CODE_FOR_reduc_smax_v8sf = 4285, CODE_FOR_reduc_smin_v8sf = 4286, CODE_FOR_reduc_smax_v4df = 4287, CODE_FOR_reduc_smin_v4df = 4288, CODE_FOR_reduc_smax_v4sf = 4289, CODE_FOR_reduc_smin_v4sf = 4290, CODE_FOR_reduc_smax_v16si = 4291, CODE_FOR_reduc_smin_v16si = 4292, CODE_FOR_reduc_smax_v8di = 4293, CODE_FOR_reduc_smin_v8di = 4294, CODE_FOR_reduc_smax_v16sf = 4295, CODE_FOR_reduc_smin_v16sf = 4296, CODE_FOR_reduc_smax_v8df = 4297, CODE_FOR_reduc_smin_v8df = 4298, CODE_FOR_reduc_umax_v16si = 4299, CODE_FOR_reduc_umin_v16si = 4300, CODE_FOR_reduc_umax_v8di = 4301, CODE_FOR_reduc_umin_v8di = 4302, CODE_FOR_reduc_umax_v32qi = 4303, CODE_FOR_reduc_umin_v32qi = 4304, CODE_FOR_reduc_umax_v16hi = 4305, CODE_FOR_reduc_umin_v16hi = 4306, CODE_FOR_reduc_umax_v8si = 4307, CODE_FOR_reduc_umin_v8si = 4308, CODE_FOR_reduc_umax_v4di = 4309, CODE_FOR_reduc_umin_v4di = 4310, CODE_FOR_reduc_umin_v8hi = 4311, CODE_FOR_vcondv64qiv16sf = 4312, CODE_FOR_vcondv32hiv16sf = 4313, CODE_FOR_vcondv16siv16sf = 4314, CODE_FOR_vcondv8div16sf = 4315, CODE_FOR_vcondv16sfv16sf = 4316, CODE_FOR_vcondv8dfv16sf = 4317, CODE_FOR_vcondv64qiv8df = 4318, CODE_FOR_vcondv32hiv8df = 4319, CODE_FOR_vcondv16siv8df = 4320, CODE_FOR_vcondv8div8df = 4321, CODE_FOR_vcondv16sfv8df = 4322, CODE_FOR_vcondv8dfv8df = 4323, CODE_FOR_vcondv32qiv8sf = 4324, CODE_FOR_vcondv32qiv4df = 4325, CODE_FOR_vcondv16hiv8sf = 4326, CODE_FOR_vcondv16hiv4df = 4327, CODE_FOR_vcondv8siv8sf = 4328, CODE_FOR_vcondv8siv4df = 4329, CODE_FOR_vcondv4div8sf = 4330, CODE_FOR_vcondv4div4df = 4331, CODE_FOR_vcondv8sfv8sf = 4332, CODE_FOR_vcondv8sfv4df = 4333, CODE_FOR_vcondv4dfv8sf = 4334, CODE_FOR_vcondv4dfv4df = 4335, CODE_FOR_vcondv16qiv4sf = 4336, CODE_FOR_vcondv16qiv2df = 4337, CODE_FOR_vcondv8hiv4sf = 4338, CODE_FOR_vcondv8hiv2df = 4339, CODE_FOR_vcondv4siv4sf = 4340, CODE_FOR_vcondv4siv2df = 4341, CODE_FOR_vcondv2div4sf = 4342, CODE_FOR_vcondv2div2df = 4343, CODE_FOR_vcondv4sfv4sf = 4344, CODE_FOR_vcondv4sfv2df = 4345, CODE_FOR_vcondv2dfv4sf = 4346, CODE_FOR_vcondv2dfv2df = 4347, CODE_FOR_andv8sf3 = 4348, CODE_FOR_iorv8sf3 = 4349, CODE_FOR_xorv8sf3 = 4350, CODE_FOR_andv4sf3 = 4351, CODE_FOR_iorv4sf3 = 4352, CODE_FOR_xorv4sf3 = 4353, CODE_FOR_andv4df3 = 4354, CODE_FOR_iorv4df3 = 4355, CODE_FOR_xorv4df3 = 4356, CODE_FOR_andv2df3 = 4357, CODE_FOR_iorv2df3 = 4358, CODE_FOR_xorv2df3 = 4359, CODE_FOR_andv16sf3 = 4360, CODE_FOR_xorv16sf3 = 4361, CODE_FOR_andv8df3 = 4362, CODE_FOR_xorv8df3 = 4363, CODE_FOR_copysignv16sf3 = 4364, CODE_FOR_copysignv8sf3 = 4365, CODE_FOR_copysignv4sf3 = 4366, CODE_FOR_copysignv8df3 = 4367, CODE_FOR_copysignv4df3 = 4368, CODE_FOR_copysignv2df3 = 4369, CODE_FOR_andtf3 = 4370, CODE_FOR_iortf3 = 4371, CODE_FOR_xortf3 = 4372, CODE_FOR_fmasf4 = 4373, CODE_FOR_fmadf4 = 4374, CODE_FOR_fmav4sf4 = 4375, CODE_FOR_fmav2df4 = 4376, CODE_FOR_fmav8sf4 = 4377, CODE_FOR_fmav4df4 = 4378, CODE_FOR_fmav16sf4 = 4379, CODE_FOR_fmav8df4 = 4380, CODE_FOR_fmssf4 = 4381, CODE_FOR_fmsdf4 = 4382, CODE_FOR_fmsv4sf4 = 4383, CODE_FOR_fmsv2df4 = 4384, CODE_FOR_fmsv8sf4 = 4385, CODE_FOR_fmsv4df4 = 4386, CODE_FOR_fmsv16sf4 = 4387, CODE_FOR_fmsv8df4 = 4388, CODE_FOR_fnmasf4 = 4389, CODE_FOR_fnmadf4 = 4390, CODE_FOR_fnmav4sf4 = 4391, CODE_FOR_fnmav2df4 = 4392, CODE_FOR_fnmav8sf4 = 4393, CODE_FOR_fnmav4df4 = 4394, CODE_FOR_fnmav16sf4 = 4395, CODE_FOR_fnmav8df4 = 4396, CODE_FOR_fnmssf4 = 4397, CODE_FOR_fnmsdf4 = 4398, CODE_FOR_fnmsv4sf4 = 4399, CODE_FOR_fnmsv2df4 = 4400, CODE_FOR_fnmsv8sf4 = 4401, CODE_FOR_fnmsv4df4 = 4402, CODE_FOR_fnmsv16sf4 = 4403, CODE_FOR_fnmsv8df4 = 4404, CODE_FOR_fma4i_fmadd_sf = 4405, CODE_FOR_fma4i_fmadd_df = 4406, CODE_FOR_fma4i_fmadd_v4sf = 4407, CODE_FOR_fma4i_fmadd_v2df = 4408, CODE_FOR_fma4i_fmadd_v8sf = 4409, CODE_FOR_fma4i_fmadd_v4df = 4410, CODE_FOR_fma4i_fmadd_v16sf = 4411, CODE_FOR_fma4i_fmadd_v8df = 4412, CODE_FOR_avx512f_fmadd_v16sf_maskz = 4413, CODE_FOR_avx512f_fmadd_v16sf_maskz_round = 4414, CODE_FOR_avx512f_fmadd_v8df_maskz = 4415, CODE_FOR_avx512f_fmadd_v8df_maskz_round = 4416, CODE_FOR_fmaddsub_v16sf = 4417, CODE_FOR_fmaddsub_v8sf = 4418, CODE_FOR_fmaddsub_v4sf = 4419, CODE_FOR_fmaddsub_v8df = 4420, CODE_FOR_fmaddsub_v4df = 4421, CODE_FOR_fmaddsub_v2df = 4422, CODE_FOR_avx512f_fmaddsub_v16sf_maskz = 4423, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round = 4424, CODE_FOR_avx512f_fmaddsub_v8df_maskz = 4425, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round = 4426, CODE_FOR_fmai_vmfmadd_v4sf = 4427, CODE_FOR_fmai_vmfmadd_v4sf_round = 4428, CODE_FOR_fmai_vmfmadd_v2df = 4429, CODE_FOR_fmai_vmfmadd_v2df_round = 4430, CODE_FOR_fma4i_vmfmadd_v4sf = 4431, CODE_FOR_fma4i_vmfmadd_v2df = 4432, CODE_FOR_floatunsv16siv16sf2 = 4433, CODE_FOR_floatunsv8siv8sf2 = 4434, CODE_FOR_floatunsv4siv4sf2 = 4435, CODE_FOR_fixuns_truncv16sfv16si2 = 4436, CODE_FOR_fixuns_truncv8sfv8si2 = 4437, CODE_FOR_fixuns_truncv4sfv4si2 = 4438, CODE_FOR_avx_cvtpd2dq256_2 = 4439, CODE_FOR_sse2_cvtpd2dq = 4440, CODE_FOR_avx_cvttpd2dq256_2 = 4441, CODE_FOR_sse2_cvttpd2dq = 4442, CODE_FOR_sse2_cvtpd2ps = 4443, CODE_FOR_vec_unpacks_hi_v4sf = 4444, CODE_FOR_vec_unpacks_hi_v8sf = 4445, CODE_FOR_vec_unpacks_hi_v16sf = 4446, CODE_FOR_vec_unpacks_lo_v4sf = 4447, CODE_FOR_vec_unpacks_lo_v8sf = 4448, CODE_FOR_vec_unpacks_float_hi_v32hi = 4449, CODE_FOR_vec_unpacks_float_hi_v16hi = 4450, CODE_FOR_vec_unpacks_float_hi_v8hi = 4451, CODE_FOR_vec_unpacks_float_lo_v32hi = 4452, CODE_FOR_vec_unpacks_float_lo_v16hi = 4453, CODE_FOR_vec_unpacks_float_lo_v8hi = 4454, CODE_FOR_vec_unpacku_float_hi_v32hi = 4455, CODE_FOR_vec_unpacku_float_hi_v16hi = 4456, CODE_FOR_vec_unpacku_float_hi_v8hi = 4457, CODE_FOR_vec_unpacku_float_lo_v32hi = 4458, CODE_FOR_vec_unpacku_float_lo_v16hi = 4459, CODE_FOR_vec_unpacku_float_lo_v8hi = 4460, CODE_FOR_vec_unpacks_float_hi_v4si = 4461, CODE_FOR_vec_unpacks_float_lo_v4si = 4462, CODE_FOR_vec_unpacks_float_hi_v8si = 4463, CODE_FOR_vec_unpacks_float_lo_v8si = 4464, CODE_FOR_vec_unpacks_float_hi_v16si = 4465, CODE_FOR_vec_unpacks_float_lo_v16si = 4466, CODE_FOR_vec_unpacku_float_hi_v4si = 4467, CODE_FOR_vec_unpacku_float_lo_v4si = 4468, CODE_FOR_vec_unpacku_float_hi_v8si = 4469, CODE_FOR_vec_unpacku_float_hi_v16si = 4470, CODE_FOR_vec_unpacku_float_lo_v8si = 4471, CODE_FOR_vec_unpacku_float_lo_v16si = 4472, CODE_FOR_vec_pack_trunc_v8df = 4473, CODE_FOR_vec_pack_trunc_v4df = 4474, CODE_FOR_vec_pack_trunc_v2df = 4475, CODE_FOR_vec_pack_sfix_trunc_v8df = 4476, CODE_FOR_vec_pack_sfix_trunc_v4df = 4477, CODE_FOR_vec_pack_sfix_trunc_v2df = 4478, CODE_FOR_vec_pack_ufix_trunc_v8df = 4479, CODE_FOR_vec_pack_ufix_trunc_v4df = 4480, CODE_FOR_vec_pack_ufix_trunc_v2df = 4481, CODE_FOR_vec_pack_sfix_v4df = 4482, CODE_FOR_vec_pack_sfix_v2df = 4483, CODE_FOR_sse_movhlps_exp = 4484, CODE_FOR_sse_movlhps_exp = 4485, CODE_FOR_vec_interleave_highv8sf = 4486, CODE_FOR_vec_interleave_lowv8sf = 4487, CODE_FOR_avx_shufps256 = 4488, CODE_FOR_sse_shufps = 4489, CODE_FOR_sse_loadhps_exp = 4490, CODE_FOR_sse_loadlps_exp = 4491, CODE_FOR_vec_initv16qi = 4492, CODE_FOR_vec_initv8hi = 4493, CODE_FOR_vec_initv4si = 4494, CODE_FOR_vec_initv2di = 4495, CODE_FOR_vec_initv4sf = 4496, CODE_FOR_vec_initv2df = 4497, CODE_FOR_vec_setv32qi = 4500, CODE_FOR_vec_setv16qi = 4501, CODE_FOR_vec_setv16hi = 4502, CODE_FOR_vec_setv8hi = 4503, CODE_FOR_vec_setv16si = 4504, CODE_FOR_vec_setv8si = 4505, CODE_FOR_vec_setv4si = 4506, CODE_FOR_vec_setv8di = 4507, CODE_FOR_vec_setv4di = 4508, CODE_FOR_vec_setv2di = 4509, CODE_FOR_vec_setv16sf = 4510, CODE_FOR_vec_setv8sf = 4511, CODE_FOR_vec_setv4sf = 4512, CODE_FOR_vec_setv8df = 4513, CODE_FOR_vec_setv4df = 4514, CODE_FOR_vec_setv2df = 4515, CODE_FOR_avx512f_vextractf32x4_mask = 4519, CODE_FOR_avx512f_vextracti32x4_mask = 4520, CODE_FOR_avx512f_vextractf64x4_mask = 4521, CODE_FOR_avx512f_vextracti64x4_mask = 4522, CODE_FOR_avx_vextractf128v32qi = 4525, CODE_FOR_avx_vextractf128v16hi = 4526, CODE_FOR_avx_vextractf128v8si = 4527, CODE_FOR_avx_vextractf128v4di = 4528, CODE_FOR_avx_vextractf128v8sf = 4529, CODE_FOR_avx_vextractf128v4df = 4530, CODE_FOR_vec_extractv32qi = 4541, CODE_FOR_vec_extractv16qi = 4542, CODE_FOR_vec_extractv16hi = 4543, CODE_FOR_vec_extractv8hi = 4544, CODE_FOR_vec_extractv16si = 4545, CODE_FOR_vec_extractv8si = 4546, CODE_FOR_vec_extractv4si = 4547, CODE_FOR_vec_extractv8di = 4548, CODE_FOR_vec_extractv4di = 4549, CODE_FOR_vec_extractv2di = 4550, CODE_FOR_vec_extractv16sf = 4551, CODE_FOR_vec_extractv8sf = 4552, CODE_FOR_vec_extractv4sf = 4553, CODE_FOR_vec_extractv8df = 4554, CODE_FOR_vec_extractv4df = 4555, CODE_FOR_vec_extractv2df = 4556, CODE_FOR_vec_interleave_highv4df = 4557, CODE_FOR_vec_interleave_highv2df = 4558, CODE_FOR_avx512f_movddup512 = 4559, CODE_FOR_avx512f_movddup512_mask = 4560, CODE_FOR_avx512f_unpcklpd512 = 4561, CODE_FOR_avx512f_unpcklpd512_mask = 4562, CODE_FOR_avx_movddup256 = 4563, CODE_FOR_avx_unpcklpd256 = 4564, CODE_FOR_vec_interleave_lowv4df = 4565, CODE_FOR_vec_interleave_lowv2df = 4566, CODE_FOR_avx512f_vternlogv16si_maskz = 4569, CODE_FOR_avx512f_vternlogv8di_maskz = 4570, CODE_FOR_avx512f_shufps512_mask = 4571, CODE_FOR_avx512f_fixupimmv16sf_maskz = 4572, CODE_FOR_avx512f_fixupimmv16sf_maskz_round = 4573, CODE_FOR_avx512f_fixupimmv8df_maskz = 4574, CODE_FOR_avx512f_fixupimmv8df_maskz_round = 4575, CODE_FOR_avx512f_sfixupimmv4sf_maskz = 4576, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round = 4577, CODE_FOR_avx512f_sfixupimmv2df_maskz = 4578, CODE_FOR_avx512f_sfixupimmv2df_maskz_round = 4579, CODE_FOR_avx512f_shufpd512_mask = 4580, CODE_FOR_avx_shufpd256 = 4581, CODE_FOR_sse2_shufpd = 4582, CODE_FOR_sse2_loadhpd_exp = 4585, CODE_FOR_sse2_loadlpd_exp = 4587, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store = 4589, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store = 4590, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store = 4591, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store = 4592, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store = 4593, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store = 4594, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store = 4595, CODE_FOR_avx512f_truncatev8div8si2_mask_store = 4596, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store = 4597, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store = 4598, CODE_FOR_avx512f_truncatev8div8hi2_mask_store = 4599, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store = 4600, CODE_FOR_negv32qi2 = 4601, CODE_FOR_negv16qi2 = 4602, CODE_FOR_negv16hi2 = 4603, CODE_FOR_negv8hi2 = 4604, CODE_FOR_negv16si2 = 4605, CODE_FOR_negv8si2 = 4606, CODE_FOR_negv4si2 = 4607, CODE_FOR_negv8di2 = 4608, CODE_FOR_negv4di2 = 4609, CODE_FOR_negv2di2 = 4610, CODE_FOR_addv32qi3 = 4611, CODE_FOR_subv32qi3 = 4612, CODE_FOR_addv16qi3 = 4613, #define CODE_FOR_addv16qi3_mask CODE_FOR_nothing CODE_FOR_subv16qi3 = 4614, #define CODE_FOR_subv16qi3_mask CODE_FOR_nothing CODE_FOR_addv16hi3 = 4615, #define CODE_FOR_addv16hi3_mask CODE_FOR_nothing CODE_FOR_subv16hi3 = 4616, #define CODE_FOR_subv16hi3_mask CODE_FOR_nothing CODE_FOR_addv8hi3 = 4617, #define CODE_FOR_addv8hi3_mask CODE_FOR_nothing CODE_FOR_subv8hi3 = 4618, #define CODE_FOR_subv8hi3_mask CODE_FOR_nothing CODE_FOR_addv16si3 = 4619, CODE_FOR_addv16si3_mask = 4620, CODE_FOR_subv16si3 = 4621, CODE_FOR_subv16si3_mask = 4622, CODE_FOR_addv8si3 = 4623, #define CODE_FOR_addv8si3_mask CODE_FOR_nothing CODE_FOR_subv8si3 = 4624, #define CODE_FOR_subv8si3_mask CODE_FOR_nothing CODE_FOR_addv4si3 = 4625, #define CODE_FOR_addv4si3_mask CODE_FOR_nothing CODE_FOR_subv4si3 = 4626, #define CODE_FOR_subv4si3_mask CODE_FOR_nothing CODE_FOR_addv8di3 = 4627, CODE_FOR_addv8di3_mask = 4628, CODE_FOR_subv8di3 = 4629, CODE_FOR_subv8di3_mask = 4630, CODE_FOR_addv4di3 = 4631, #define CODE_FOR_addv4di3_mask CODE_FOR_nothing CODE_FOR_subv4di3 = 4632, #define CODE_FOR_subv4di3_mask CODE_FOR_nothing CODE_FOR_addv2di3 = 4633, #define CODE_FOR_addv2di3_mask CODE_FOR_nothing CODE_FOR_subv2di3 = 4634, #define CODE_FOR_subv2di3_mask CODE_FOR_nothing CODE_FOR_avx2_ssaddv32qi3 = 4635, CODE_FOR_avx2_usaddv32qi3 = 4636, CODE_FOR_avx2_sssubv32qi3 = 4637, CODE_FOR_avx2_ussubv32qi3 = 4638, CODE_FOR_sse2_ssaddv16qi3 = 4639, CODE_FOR_sse2_usaddv16qi3 = 4640, CODE_FOR_sse2_sssubv16qi3 = 4641, CODE_FOR_sse2_ussubv16qi3 = 4642, CODE_FOR_avx2_ssaddv16hi3 = 4643, CODE_FOR_avx2_usaddv16hi3 = 4644, CODE_FOR_avx2_sssubv16hi3 = 4645, CODE_FOR_avx2_ussubv16hi3 = 4646, CODE_FOR_sse2_ssaddv8hi3 = 4647, CODE_FOR_sse2_usaddv8hi3 = 4648, CODE_FOR_sse2_sssubv8hi3 = 4649, CODE_FOR_sse2_ussubv8hi3 = 4650, CODE_FOR_mulv32qi3 = 4651, CODE_FOR_mulv16qi3 = 4652, CODE_FOR_mulv16hi3 = 4653, CODE_FOR_mulv8hi3 = 4654, CODE_FOR_smulv16hi3_highpart = 4655, CODE_FOR_umulv16hi3_highpart = 4656, CODE_FOR_smulv8hi3_highpart = 4657, CODE_FOR_umulv8hi3_highpart = 4658, CODE_FOR_vec_widen_umult_even_v16si = 4659, CODE_FOR_vec_widen_umult_even_v16si_mask = 4660, CODE_FOR_vec_widen_umult_even_v8si = 4661, CODE_FOR_vec_widen_umult_even_v4si = 4662, CODE_FOR_vec_widen_smult_even_v16si = 4663, CODE_FOR_vec_widen_smult_even_v16si_mask = 4664, CODE_FOR_vec_widen_smult_even_v8si = 4665, CODE_FOR_sse4_1_mulv2siv2di3 = 4666, CODE_FOR_avx2_pmaddwd = 4667, CODE_FOR_sse2_pmaddwd = 4668, CODE_FOR_mulv16si3 = 4669, CODE_FOR_mulv16si3_mask = 4670, CODE_FOR_mulv8si3 = 4671, #define CODE_FOR_mulv8si3_mask CODE_FOR_nothing CODE_FOR_mulv4si3 = 4672, #define CODE_FOR_mulv4si3_mask CODE_FOR_nothing CODE_FOR_mulv8di3 = 4673, CODE_FOR_mulv4di3 = 4674, CODE_FOR_mulv2di3 = 4675, CODE_FOR_vec_widen_smult_hi_v32qi = 4676, CODE_FOR_vec_widen_umult_hi_v32qi = 4677, CODE_FOR_vec_widen_smult_hi_v16qi = 4678, CODE_FOR_vec_widen_umult_hi_v16qi = 4679, CODE_FOR_vec_widen_smult_hi_v16hi = 4680, CODE_FOR_vec_widen_umult_hi_v16hi = 4681, CODE_FOR_vec_widen_smult_hi_v8hi = 4682, CODE_FOR_vec_widen_umult_hi_v8hi = 4683, CODE_FOR_vec_widen_smult_hi_v8si = 4684, CODE_FOR_vec_widen_umult_hi_v8si = 4685, CODE_FOR_vec_widen_smult_hi_v4si = 4686, CODE_FOR_vec_widen_umult_hi_v4si = 4687, CODE_FOR_vec_widen_smult_lo_v32qi = 4688, CODE_FOR_vec_widen_umult_lo_v32qi = 4689, CODE_FOR_vec_widen_smult_lo_v16qi = 4690, CODE_FOR_vec_widen_umult_lo_v16qi = 4691, CODE_FOR_vec_widen_smult_lo_v16hi = 4692, CODE_FOR_vec_widen_umult_lo_v16hi = 4693, CODE_FOR_vec_widen_smult_lo_v8hi = 4694, CODE_FOR_vec_widen_umult_lo_v8hi = 4695, CODE_FOR_vec_widen_smult_lo_v8si = 4696, CODE_FOR_vec_widen_umult_lo_v8si = 4697, CODE_FOR_vec_widen_smult_lo_v4si = 4698, CODE_FOR_vec_widen_umult_lo_v4si = 4699, CODE_FOR_vec_widen_smult_even_v4si = 4700, CODE_FOR_vec_widen_smult_odd_v16si = 4701, CODE_FOR_vec_widen_umult_odd_v16si = 4702, CODE_FOR_vec_widen_smult_odd_v8si = 4703, CODE_FOR_vec_widen_umult_odd_v8si = 4704, CODE_FOR_vec_widen_smult_odd_v4si = 4705, CODE_FOR_vec_widen_umult_odd_v4si = 4706, CODE_FOR_sdot_prodv16hi = 4707, CODE_FOR_sdot_prodv8hi = 4708, CODE_FOR_sdot_prodv4si = 4709, CODE_FOR_vec_shl_v16qi = 4710, CODE_FOR_vec_shl_v8hi = 4711, CODE_FOR_vec_shl_v4si = 4712, CODE_FOR_vec_shl_v2di = 4713, CODE_FOR_vec_shr_v16qi = 4714, CODE_FOR_vec_shr_v8hi = 4715, CODE_FOR_vec_shr_v4si = 4716, CODE_FOR_vec_shr_v2di = 4717, CODE_FOR_smaxv32qi3 = 4718, CODE_FOR_sminv32qi3 = 4719, CODE_FOR_umaxv32qi3 = 4720, CODE_FOR_uminv32qi3 = 4721, CODE_FOR_smaxv16hi3 = 4722, #define CODE_FOR_smaxv16hi3_round CODE_FOR_nothing #define CODE_FOR_smaxv16hi3_mask CODE_FOR_nothing #define CODE_FOR_smaxv16hi3_mask_round CODE_FOR_nothing CODE_FOR_sminv16hi3 = 4723, #define CODE_FOR_sminv16hi3_round CODE_FOR_nothing #define CODE_FOR_sminv16hi3_mask CODE_FOR_nothing #define CODE_FOR_sminv16hi3_mask_round CODE_FOR_nothing CODE_FOR_umaxv16hi3 = 4724, #define CODE_FOR_umaxv16hi3_round CODE_FOR_nothing #define CODE_FOR_umaxv16hi3_mask CODE_FOR_nothing #define CODE_FOR_umaxv16hi3_mask_round CODE_FOR_nothing CODE_FOR_uminv16hi3 = 4725, #define CODE_FOR_uminv16hi3_round CODE_FOR_nothing #define CODE_FOR_uminv16hi3_mask CODE_FOR_nothing #define CODE_FOR_uminv16hi3_mask_round CODE_FOR_nothing CODE_FOR_smaxv8si3 = 4726, #define CODE_FOR_smaxv8si3_round CODE_FOR_nothing #define CODE_FOR_smaxv8si3_mask CODE_FOR_nothing #define CODE_FOR_smaxv8si3_mask_round CODE_FOR_nothing CODE_FOR_sminv8si3 = 4727, #define CODE_FOR_sminv8si3_round CODE_FOR_nothing #define CODE_FOR_sminv8si3_mask CODE_FOR_nothing #define CODE_FOR_sminv8si3_mask_round CODE_FOR_nothing CODE_FOR_umaxv8si3 = 4728, #define CODE_FOR_umaxv8si3_round CODE_FOR_nothing #define CODE_FOR_umaxv8si3_mask CODE_FOR_nothing #define CODE_FOR_umaxv8si3_mask_round CODE_FOR_nothing CODE_FOR_uminv8si3 = 4729, #define CODE_FOR_uminv8si3_round CODE_FOR_nothing #define CODE_FOR_uminv8si3_mask CODE_FOR_nothing #define CODE_FOR_uminv8si3_mask_round CODE_FOR_nothing CODE_FOR_smaxv8di3 = 4730, #define CODE_FOR_smaxv8di3_round CODE_FOR_nothing CODE_FOR_smaxv8di3_mask = 4731, #define CODE_FOR_smaxv8di3_mask_round CODE_FOR_nothing CODE_FOR_sminv8di3 = 4732, #define CODE_FOR_sminv8di3_round CODE_FOR_nothing CODE_FOR_sminv8di3_mask = 4733, #define CODE_FOR_sminv8di3_mask_round CODE_FOR_nothing CODE_FOR_umaxv8di3 = 4734, #define CODE_FOR_umaxv8di3_round CODE_FOR_nothing CODE_FOR_umaxv8di3_mask = 4735, #define CODE_FOR_umaxv8di3_mask_round CODE_FOR_nothing CODE_FOR_uminv8di3 = 4736, #define CODE_FOR_uminv8di3_round CODE_FOR_nothing CODE_FOR_uminv8di3_mask = 4737, #define CODE_FOR_uminv8di3_mask_round CODE_FOR_nothing CODE_FOR_smaxv16si3 = 4738, #define CODE_FOR_smaxv16si3_round CODE_FOR_nothing CODE_FOR_smaxv16si3_mask = 4739, #define CODE_FOR_smaxv16si3_mask_round CODE_FOR_nothing CODE_FOR_sminv16si3 = 4740, #define CODE_FOR_sminv16si3_round CODE_FOR_nothing CODE_FOR_sminv16si3_mask = 4741, #define CODE_FOR_sminv16si3_mask_round CODE_FOR_nothing CODE_FOR_umaxv16si3 = 4742, #define CODE_FOR_umaxv16si3_round CODE_FOR_nothing CODE_FOR_umaxv16si3_mask = 4743, #define CODE_FOR_umaxv16si3_mask_round CODE_FOR_nothing CODE_FOR_uminv16si3 = 4744, #define CODE_FOR_uminv16si3_round CODE_FOR_nothing CODE_FOR_uminv16si3_mask = 4745, #define CODE_FOR_uminv16si3_mask_round CODE_FOR_nothing CODE_FOR_smaxv4di3 = 4746, CODE_FOR_sminv4di3 = 4747, CODE_FOR_umaxv4di3 = 4748, CODE_FOR_uminv4di3 = 4749, CODE_FOR_smaxv2di3 = 4750, CODE_FOR_sminv2di3 = 4751, CODE_FOR_umaxv2di3 = 4752, CODE_FOR_uminv2di3 = 4753, CODE_FOR_smaxv16qi3 = 4754, CODE_FOR_sminv16qi3 = 4755, CODE_FOR_smaxv8hi3 = 4756, CODE_FOR_sminv8hi3 = 4757, CODE_FOR_smaxv4si3 = 4758, CODE_FOR_sminv4si3 = 4759, CODE_FOR_umaxv16qi3 = 4760, CODE_FOR_uminv16qi3 = 4761, CODE_FOR_umaxv8hi3 = 4762, CODE_FOR_uminv8hi3 = 4763, CODE_FOR_umaxv4si3 = 4764, CODE_FOR_uminv4si3 = 4765, CODE_FOR_avx2_eqv32qi3 = 4766, CODE_FOR_avx2_eqv16hi3 = 4767, CODE_FOR_avx2_eqv8si3 = 4768, CODE_FOR_avx2_eqv4di3 = 4769, CODE_FOR_avx512f_eqv16si3 = 4770, CODE_FOR_avx512f_eqv16si3_mask = 4771, CODE_FOR_avx512f_eqv8di3 = 4772, CODE_FOR_avx512f_eqv8di3_mask = 4773, CODE_FOR_sse2_eqv16qi3 = 4774, CODE_FOR_sse2_eqv8hi3 = 4775, CODE_FOR_sse2_eqv4si3 = 4776, CODE_FOR_sse4_1_eqv2di3 = 4777, CODE_FOR_vcondv64qiv64qi = 4778, CODE_FOR_vcondv32hiv64qi = 4779, CODE_FOR_vcondv16siv64qi = 4780, CODE_FOR_vcondv8div64qi = 4781, CODE_FOR_vcondv16sfv64qi = 4782, CODE_FOR_vcondv8dfv64qi = 4783, CODE_FOR_vcondv64qiv32hi = 4784, CODE_FOR_vcondv32hiv32hi = 4785, CODE_FOR_vcondv16siv32hi = 4786, CODE_FOR_vcondv8div32hi = 4787, CODE_FOR_vcondv16sfv32hi = 4788, CODE_FOR_vcondv8dfv32hi = 4789, CODE_FOR_vcondv64qiv16si = 4790, CODE_FOR_vcondv32hiv16si = 4791, CODE_FOR_vcondv16siv16si = 4792, CODE_FOR_vcondv8div16si = 4793, CODE_FOR_vcondv16sfv16si = 4794, CODE_FOR_vcondv8dfv16si = 4795, CODE_FOR_vcondv64qiv8di = 4796, CODE_FOR_vcondv32hiv8di = 4797, CODE_FOR_vcondv16siv8di = 4798, CODE_FOR_vcondv8div8di = 4799, CODE_FOR_vcondv16sfv8di = 4800, CODE_FOR_vcondv8dfv8di = 4801, CODE_FOR_vcondv32qiv32qi = 4802, CODE_FOR_vcondv16hiv32qi = 4803, CODE_FOR_vcondv8siv32qi = 4804, CODE_FOR_vcondv4div32qi = 4805, CODE_FOR_vcondv8sfv32qi = 4806, CODE_FOR_vcondv4dfv32qi = 4807, CODE_FOR_vcondv32qiv16hi = 4808, CODE_FOR_vcondv16hiv16hi = 4809, CODE_FOR_vcondv8siv16hi = 4810, CODE_FOR_vcondv4div16hi = 4811, CODE_FOR_vcondv8sfv16hi = 4812, CODE_FOR_vcondv4dfv16hi = 4813, CODE_FOR_vcondv32qiv8si = 4814, CODE_FOR_vcondv16hiv8si = 4815, CODE_FOR_vcondv8siv8si = 4816, CODE_FOR_vcondv4div8si = 4817, CODE_FOR_vcondv8sfv8si = 4818, CODE_FOR_vcondv4dfv8si = 4819, CODE_FOR_vcondv32qiv4di = 4820, CODE_FOR_vcondv16hiv4di = 4821, CODE_FOR_vcondv8siv4di = 4822, CODE_FOR_vcondv4div4di = 4823, CODE_FOR_vcondv8sfv4di = 4824, CODE_FOR_vcondv4dfv4di = 4825, CODE_FOR_vcondv16qiv16qi = 4826, CODE_FOR_vcondv16qiv8hi = 4827, CODE_FOR_vcondv16qiv4si = 4828, CODE_FOR_vcondv8hiv16qi = 4829, CODE_FOR_vcondv8hiv8hi = 4830, CODE_FOR_vcondv8hiv4si = 4831, CODE_FOR_vcondv4siv16qi = 4832, CODE_FOR_vcondv4siv8hi = 4833, CODE_FOR_vcondv4siv4si = 4834, CODE_FOR_vcondv2div16qi = 4835, CODE_FOR_vcondv2div8hi = 4836, CODE_FOR_vcondv2div4si = 4837, CODE_FOR_vcondv4sfv16qi = 4838, CODE_FOR_vcondv4sfv8hi = 4839, CODE_FOR_vcondv4sfv4si = 4840, CODE_FOR_vcondv2dfv16qi = 4841, CODE_FOR_vcondv2dfv8hi = 4842, CODE_FOR_vcondv2dfv4si = 4843, CODE_FOR_vcondv2div2di = 4844, CODE_FOR_vcondv2dfv2di = 4845, CODE_FOR_vconduv64qiv64qi = 4846, CODE_FOR_vconduv32hiv64qi = 4847, CODE_FOR_vconduv16siv64qi = 4848, CODE_FOR_vconduv8div64qi = 4849, CODE_FOR_vconduv16sfv64qi = 4850, CODE_FOR_vconduv8dfv64qi = 4851, CODE_FOR_vconduv64qiv32hi = 4852, CODE_FOR_vconduv32hiv32hi = 4853, CODE_FOR_vconduv16siv32hi = 4854, CODE_FOR_vconduv8div32hi = 4855, CODE_FOR_vconduv16sfv32hi = 4856, CODE_FOR_vconduv8dfv32hi = 4857, CODE_FOR_vconduv64qiv16si = 4858, CODE_FOR_vconduv32hiv16si = 4859, CODE_FOR_vconduv16siv16si = 4860, CODE_FOR_vconduv8div16si = 4861, CODE_FOR_vconduv16sfv16si = 4862, CODE_FOR_vconduv8dfv16si = 4863, CODE_FOR_vconduv64qiv8di = 4864, CODE_FOR_vconduv32hiv8di = 4865, CODE_FOR_vconduv16siv8di = 4866, CODE_FOR_vconduv8div8di = 4867, CODE_FOR_vconduv16sfv8di = 4868, CODE_FOR_vconduv8dfv8di = 4869, CODE_FOR_vconduv32qiv32qi = 4870, CODE_FOR_vconduv16hiv32qi = 4871, CODE_FOR_vconduv8siv32qi = 4872, CODE_FOR_vconduv4div32qi = 4873, CODE_FOR_vconduv8sfv32qi = 4874, CODE_FOR_vconduv4dfv32qi = 4875, CODE_FOR_vconduv32qiv16hi = 4876, CODE_FOR_vconduv16hiv16hi = 4877, CODE_FOR_vconduv8siv16hi = 4878, CODE_FOR_vconduv4div16hi = 4879, CODE_FOR_vconduv8sfv16hi = 4880, CODE_FOR_vconduv4dfv16hi = 4881, CODE_FOR_vconduv32qiv8si = 4882, CODE_FOR_vconduv16hiv8si = 4883, CODE_FOR_vconduv8siv8si = 4884, CODE_FOR_vconduv4div8si = 4885, CODE_FOR_vconduv8sfv8si = 4886, CODE_FOR_vconduv4dfv8si = 4887, CODE_FOR_vconduv32qiv4di = 4888, CODE_FOR_vconduv16hiv4di = 4889, CODE_FOR_vconduv8siv4di = 4890, CODE_FOR_vconduv4div4di = 4891, CODE_FOR_vconduv8sfv4di = 4892, CODE_FOR_vconduv4dfv4di = 4893, CODE_FOR_vconduv16qiv16qi = 4894, CODE_FOR_vconduv16qiv8hi = 4895, CODE_FOR_vconduv16qiv4si = 4896, CODE_FOR_vconduv8hiv16qi = 4897, CODE_FOR_vconduv8hiv8hi = 4898, CODE_FOR_vconduv8hiv4si = 4899, CODE_FOR_vconduv4siv16qi = 4900, CODE_FOR_vconduv4siv8hi = 4901, CODE_FOR_vconduv4siv4si = 4902, CODE_FOR_vconduv2div16qi = 4903, CODE_FOR_vconduv2div8hi = 4904, CODE_FOR_vconduv2div4si = 4905, CODE_FOR_vconduv4sfv16qi = 4906, CODE_FOR_vconduv4sfv8hi = 4907, CODE_FOR_vconduv4sfv4si = 4908, CODE_FOR_vconduv2dfv16qi = 4909, CODE_FOR_vconduv2dfv8hi = 4910, CODE_FOR_vconduv2dfv4si = 4911, CODE_FOR_vconduv2div2di = 4912, CODE_FOR_vconduv2dfv2di = 4913, CODE_FOR_vec_permv16qi = 4914, CODE_FOR_vec_permv8hi = 4915, CODE_FOR_vec_permv4si = 4916, CODE_FOR_vec_permv2di = 4917, CODE_FOR_vec_permv4sf = 4918, CODE_FOR_vec_permv2df = 4919, CODE_FOR_vec_permv32qi = 4920, CODE_FOR_vec_permv16hi = 4921, CODE_FOR_vec_permv8si = 4922, CODE_FOR_vec_permv4di = 4923, CODE_FOR_vec_permv8sf = 4924, CODE_FOR_vec_permv4df = 4925, CODE_FOR_vec_permv16sf = 4926, CODE_FOR_vec_permv8df = 4927, CODE_FOR_vec_permv16si = 4928, CODE_FOR_vec_permv8di = 4929, CODE_FOR_vec_perm_constv4sf = 4930, CODE_FOR_vec_perm_constv4si = 4931, CODE_FOR_vec_perm_constv2df = 4932, CODE_FOR_vec_perm_constv2di = 4933, CODE_FOR_vec_perm_constv16qi = 4934, CODE_FOR_vec_perm_constv8hi = 4935, CODE_FOR_vec_perm_constv8sf = 4936, CODE_FOR_vec_perm_constv4df = 4937, CODE_FOR_vec_perm_constv8si = 4938, CODE_FOR_vec_perm_constv4di = 4939, CODE_FOR_vec_perm_constv32qi = 4940, CODE_FOR_vec_perm_constv16hi = 4941, CODE_FOR_vec_perm_constv16si = 4942, CODE_FOR_vec_perm_constv8di = 4943, CODE_FOR_vec_perm_constv16sf = 4944, CODE_FOR_vec_perm_constv8df = 4945, CODE_FOR_one_cmplv16si2 = 4946, CODE_FOR_one_cmplv8di2 = 4947, CODE_FOR_one_cmplv32qi2 = 4948, CODE_FOR_one_cmplv16qi2 = 4949, CODE_FOR_one_cmplv16hi2 = 4950, CODE_FOR_one_cmplv8hi2 = 4951, CODE_FOR_one_cmplv8si2 = 4952, CODE_FOR_one_cmplv4si2 = 4953, CODE_FOR_one_cmplv4di2 = 4954, CODE_FOR_one_cmplv2di2 = 4955, CODE_FOR_avx2_andnotv32qi3 = 4956, CODE_FOR_sse2_andnotv16qi3 = 4957, #define CODE_FOR_sse2_andnotv16qi3_mask CODE_FOR_nothing CODE_FOR_avx2_andnotv16hi3 = 4958, #define CODE_FOR_avx2_andnotv16hi3_mask CODE_FOR_nothing CODE_FOR_sse2_andnotv8hi3 = 4959, #define CODE_FOR_sse2_andnotv8hi3_mask CODE_FOR_nothing CODE_FOR_avx512f_andnotv16si3 = 4960, CODE_FOR_avx512f_andnotv16si3_mask = 4961, CODE_FOR_avx2_andnotv8si3 = 4962, #define CODE_FOR_avx2_andnotv8si3_mask CODE_FOR_nothing CODE_FOR_sse2_andnotv4si3 = 4963, #define CODE_FOR_sse2_andnotv4si3_mask CODE_FOR_nothing CODE_FOR_avx512f_andnotv8di3 = 4964, CODE_FOR_avx512f_andnotv8di3_mask = 4965, CODE_FOR_avx2_andnotv4di3 = 4966, #define CODE_FOR_avx2_andnotv4di3_mask CODE_FOR_nothing CODE_FOR_sse2_andnotv2di3 = 4967, #define CODE_FOR_sse2_andnotv2di3_mask CODE_FOR_nothing CODE_FOR_andv16si3 = 4968, CODE_FOR_iorv16si3 = 4969, CODE_FOR_xorv16si3 = 4970, CODE_FOR_andv8di3 = 4971, CODE_FOR_iorv8di3 = 4972, CODE_FOR_xorv8di3 = 4973, CODE_FOR_andv32qi3 = 4974, CODE_FOR_iorv32qi3 = 4975, CODE_FOR_xorv32qi3 = 4976, CODE_FOR_andv16qi3 = 4977, CODE_FOR_iorv16qi3 = 4978, CODE_FOR_xorv16qi3 = 4979, CODE_FOR_andv16hi3 = 4980, CODE_FOR_iorv16hi3 = 4981, CODE_FOR_xorv16hi3 = 4982, CODE_FOR_andv8hi3 = 4983, CODE_FOR_iorv8hi3 = 4984, CODE_FOR_xorv8hi3 = 4985, CODE_FOR_andv8si3 = 4986, CODE_FOR_iorv8si3 = 4987, CODE_FOR_xorv8si3 = 4988, CODE_FOR_andv4si3 = 4989, CODE_FOR_iorv4si3 = 4990, CODE_FOR_xorv4si3 = 4991, CODE_FOR_andv4di3 = 4992, CODE_FOR_iorv4di3 = 4993, CODE_FOR_xorv4di3 = 4994, CODE_FOR_andv2di3 = 4995, CODE_FOR_iorv2di3 = 4996, CODE_FOR_xorv2di3 = 4997, CODE_FOR_vec_pack_trunc_v16hi = 4998, CODE_FOR_vec_pack_trunc_v8hi = 4999, CODE_FOR_vec_pack_trunc_v8si = 5000, CODE_FOR_vec_pack_trunc_v4si = 5001, CODE_FOR_vec_pack_trunc_v8di = 5002, CODE_FOR_vec_pack_trunc_v4di = 5003, CODE_FOR_vec_pack_trunc_v2di = 5004, CODE_FOR_vec_interleave_highv32qi = 5005, CODE_FOR_vec_interleave_highv16hi = 5006, CODE_FOR_vec_interleave_highv8si = 5007, CODE_FOR_vec_interleave_highv4di = 5008, CODE_FOR_vec_interleave_lowv32qi = 5009, CODE_FOR_vec_interleave_lowv16hi = 5010, CODE_FOR_vec_interleave_lowv8si = 5011, CODE_FOR_vec_interleave_lowv4di = 5012, CODE_FOR_avx512f_vinsertf32x4_mask = 5013, CODE_FOR_avx512f_vinserti32x4_mask = 5014, CODE_FOR_avx512f_vinsertf64x4_mask = 5015, CODE_FOR_avx512f_vinserti64x4_mask = 5016, CODE_FOR_avx512f_shuf_f64x2_mask = 5017, CODE_FOR_avx512f_shuf_i64x2_mask = 5018, CODE_FOR_avx512f_shuf_f32x4_mask = 5019, CODE_FOR_avx512f_shuf_i32x4_mask = 5020, CODE_FOR_avx512f_pshufdv3_mask = 5021, CODE_FOR_avx2_pshufdv3 = 5022, CODE_FOR_sse2_pshufd = 5023, CODE_FOR_avx2_pshuflwv3 = 5024, CODE_FOR_sse2_pshuflw = 5025, CODE_FOR_avx2_pshufhwv3 = 5026, CODE_FOR_sse2_pshufhw = 5027, CODE_FOR_sse2_loadd = 5028, CODE_FOR_vec_unpacks_lo_v32qi = 5037, CODE_FOR_vec_unpacks_lo_v16qi = 5038, CODE_FOR_vec_unpacks_lo_v32hi = 5039, CODE_FOR_vec_unpacks_lo_v16hi = 5040, CODE_FOR_vec_unpacks_lo_v8hi = 5041, CODE_FOR_vec_unpacks_lo_v16si = 5042, CODE_FOR_vec_unpacks_lo_v8si = 5043, CODE_FOR_vec_unpacks_lo_v4si = 5044, CODE_FOR_vec_unpacks_hi_v32qi = 5045, CODE_FOR_vec_unpacks_hi_v16qi = 5046, CODE_FOR_vec_unpacks_hi_v32hi = 5047, CODE_FOR_vec_unpacks_hi_v16hi = 5048, CODE_FOR_vec_unpacks_hi_v8hi = 5049, CODE_FOR_vec_unpacks_hi_v16si = 5050, CODE_FOR_vec_unpacks_hi_v8si = 5051, CODE_FOR_vec_unpacks_hi_v4si = 5052, CODE_FOR_vec_unpacku_lo_v32qi = 5053, CODE_FOR_vec_unpacku_lo_v16qi = 5054, CODE_FOR_vec_unpacku_lo_v32hi = 5055, CODE_FOR_vec_unpacku_lo_v16hi = 5056, CODE_FOR_vec_unpacku_lo_v8hi = 5057, CODE_FOR_vec_unpacku_lo_v16si = 5058, CODE_FOR_vec_unpacku_lo_v8si = 5059, CODE_FOR_vec_unpacku_lo_v4si = 5060, CODE_FOR_vec_unpacku_hi_v32qi = 5061, CODE_FOR_vec_unpacku_hi_v16qi = 5062, CODE_FOR_vec_unpacku_hi_v32hi = 5063, CODE_FOR_vec_unpacku_hi_v16hi = 5064, CODE_FOR_vec_unpacku_hi_v8hi = 5065, CODE_FOR_vec_unpacku_hi_v16si = 5066, CODE_FOR_vec_unpacku_hi_v8si = 5067, CODE_FOR_vec_unpacku_hi_v4si = 5068, CODE_FOR_avx2_uavgv32qi3 = 5069, CODE_FOR_sse2_uavgv16qi3 = 5070, CODE_FOR_avx2_uavgv16hi3 = 5071, CODE_FOR_sse2_uavgv8hi3 = 5072, CODE_FOR_sse2_maskmovdqu = 5073, CODE_FOR_ssse3_pmulhrswv4hi3 = 5074, CODE_FOR_ssse3_pmulhrswv8hi3 = 5075, CODE_FOR_avx2_pmulhrswv16hi3 = 5076, CODE_FOR_absv32qi2 = 5077, CODE_FOR_absv16qi2 = 5078, CODE_FOR_absv16hi2 = 5079, CODE_FOR_absv8hi2 = 5080, CODE_FOR_absv16si2 = 5081, CODE_FOR_absv8si2 = 5082, CODE_FOR_absv4si2 = 5083, CODE_FOR_absv8di2 = 5084, CODE_FOR_avx2_pblendw = 5085, CODE_FOR_avx_roundps_sfix256 = 5086, CODE_FOR_sse4_1_roundps_sfix = 5087, CODE_FOR_avx512f_roundpd512 = 5088, CODE_FOR_avx512f_roundpd_vec_pack_sfix512 = 5089, CODE_FOR_avx_roundpd_vec_pack_sfix256 = 5090, CODE_FOR_sse4_1_roundpd_vec_pack_sfix = 5091, CODE_FOR_roundv16sf2 = 5092, CODE_FOR_roundv8sf2 = 5093, CODE_FOR_roundv4sf2 = 5094, CODE_FOR_roundv8df2 = 5095, CODE_FOR_roundv4df2 = 5096, CODE_FOR_roundv2df2 = 5097, CODE_FOR_roundv8sf2_sfix = 5098, CODE_FOR_roundv4sf2_sfix = 5099, CODE_FOR_roundv8df2_vec_pack_sfix = 5100, CODE_FOR_roundv4df2_vec_pack_sfix = 5101, CODE_FOR_roundv2df2_vec_pack_sfix = 5102, CODE_FOR_avx512pf_gatherpfv16sisf = 5107, CODE_FOR_avx512pf_gatherpfv8disf = 5108, CODE_FOR_avx512pf_gatherpfv8sidf = 5109, CODE_FOR_avx512pf_gatherpfv8didf = 5110, CODE_FOR_avx512pf_scatterpfv16sisf = 5111, CODE_FOR_avx512pf_scatterpfv8disf = 5112, CODE_FOR_avx512pf_scatterpfv8sidf = 5113, CODE_FOR_avx512pf_scatterpfv8didf = 5114, CODE_FOR_rotlv16qi3 = 5115, CODE_FOR_rotlv8hi3 = 5116, CODE_FOR_rotlv4si3 = 5117, CODE_FOR_rotlv2di3 = 5118, CODE_FOR_rotrv16qi3 = 5119, CODE_FOR_rotrv8hi3 = 5120, CODE_FOR_rotrv4si3 = 5121, CODE_FOR_rotrv2di3 = 5122, CODE_FOR_vrotrv16qi3 = 5123, CODE_FOR_vrotrv8hi3 = 5124, CODE_FOR_vrotrv4si3 = 5125, CODE_FOR_vrotrv2di3 = 5126, CODE_FOR_vrotlv16qi3 = 5127, CODE_FOR_vrotlv8hi3 = 5128, CODE_FOR_vrotlv4si3 = 5129, CODE_FOR_vrotlv2di3 = 5130, CODE_FOR_vlshrv16qi3 = 5131, CODE_FOR_vlshrv8hi3 = 5132, CODE_FOR_vlshrv4si3 = 5133, CODE_FOR_vlshrv2di3 = 5134, CODE_FOR_vlshrv16si3 = 5135, CODE_FOR_vlshrv8di3 = 5136, CODE_FOR_vlshrv8si3 = 5137, CODE_FOR_vlshrv4di3 = 5138, CODE_FOR_vashrv16qi3 = 5139, CODE_FOR_vashrv8hi3 = 5140, CODE_FOR_vashrv2di3 = 5141, CODE_FOR_vashrv4si3 = 5142, CODE_FOR_vashrv16si3 = 5143, CODE_FOR_vashrv8si3 = 5144, CODE_FOR_vashlv16qi3 = 5145, CODE_FOR_vashlv8hi3 = 5146, CODE_FOR_vashlv4si3 = 5147, CODE_FOR_vashlv2di3 = 5148, CODE_FOR_vashlv16si3 = 5149, CODE_FOR_vashlv8di3 = 5150, CODE_FOR_vashlv8si3 = 5151, CODE_FOR_vashlv4di3 = 5152, CODE_FOR_ashlv32qi3 = 5153, CODE_FOR_lshrv32qi3 = 5154, CODE_FOR_ashrv32qi3 = 5155, CODE_FOR_ashlv16qi3 = 5156, CODE_FOR_lshrv16qi3 = 5157, CODE_FOR_ashrv16qi3 = 5158, CODE_FOR_ashrv2di3 = 5159, CODE_FOR_xop_vmfrczv4sf2 = 5160, CODE_FOR_xop_vmfrczv2df2 = 5161, CODE_FOR_avx_vzeroall = 5162, CODE_FOR_avx2_permv4di = 5163, CODE_FOR_avx2_permv4df = 5164, CODE_FOR_avx512f_permv8di = 5165, CODE_FOR_avx512f_permv8df = 5166, CODE_FOR_avx512f_permv8df_mask = 5167, CODE_FOR_avx512f_permv8di_mask = 5168, CODE_FOR_avx512f_vpermilv8df = 5175, CODE_FOR_avx512f_vpermilv8df_mask = 5176, CODE_FOR_avx_vpermilv4df = 5177, #define CODE_FOR_avx_vpermilv4df_mask CODE_FOR_nothing CODE_FOR_avx_vpermilv2df = 5178, #define CODE_FOR_avx_vpermilv2df_mask CODE_FOR_nothing CODE_FOR_avx512f_vpermilv16sf = 5179, CODE_FOR_avx512f_vpermilv16sf_mask = 5180, CODE_FOR_avx_vpermilv8sf = 5181, #define CODE_FOR_avx_vpermilv8sf_mask CODE_FOR_nothing CODE_FOR_avx_vpermilv4sf = 5182, #define CODE_FOR_avx_vpermilv4sf_mask CODE_FOR_nothing CODE_FOR_avx512f_vpermi2varv16si3_maskz = 5183, CODE_FOR_avx512f_vpermi2varv16sf3_maskz = 5184, CODE_FOR_avx512f_vpermi2varv8di3_maskz = 5185, CODE_FOR_avx512f_vpermi2varv8df3_maskz = 5186, CODE_FOR_avx512f_vpermt2varv16si3_maskz = 5187, CODE_FOR_avx512f_vpermt2varv16sf3_maskz = 5188, CODE_FOR_avx512f_vpermt2varv8di3_maskz = 5189, CODE_FOR_avx512f_vpermt2varv8df3_maskz = 5190, CODE_FOR_avx_vperm2f128v8si3 = 5191, CODE_FOR_avx_vperm2f128v8sf3 = 5192, CODE_FOR_avx_vperm2f128v4df3 = 5193, CODE_FOR_avx_vinsertf128v32qi = 5194, CODE_FOR_avx_vinsertf128v16hi = 5195, CODE_FOR_avx_vinsertf128v8si = 5196, CODE_FOR_avx_vinsertf128v4di = 5197, CODE_FOR_avx_vinsertf128v8sf = 5198, CODE_FOR_avx_vinsertf128v4df = 5199, CODE_FOR_maskloadv4sf = 5200, CODE_FOR_maskloadv2df = 5201, CODE_FOR_maskloadv8sf = 5202, CODE_FOR_maskloadv4df = 5203, CODE_FOR_maskloadv4si = 5204, CODE_FOR_maskloadv2di = 5205, CODE_FOR_maskloadv8si = 5206, CODE_FOR_maskloadv4di = 5207, CODE_FOR_maskstorev4sf = 5208, CODE_FOR_maskstorev2df = 5209, CODE_FOR_maskstorev8sf = 5210, CODE_FOR_maskstorev4df = 5211, CODE_FOR_maskstorev4si = 5212, CODE_FOR_maskstorev2di = 5213, CODE_FOR_maskstorev8si = 5214, CODE_FOR_maskstorev4di = 5215, CODE_FOR_vec_initv32qi = 5219, CODE_FOR_vec_initv16hi = 5220, CODE_FOR_vec_initv8si = 5221, CODE_FOR_vec_initv4di = 5222, CODE_FOR_vec_initv8sf = 5223, CODE_FOR_vec_initv4df = 5224, CODE_FOR_vec_initv16si = 5225, CODE_FOR_vec_initv16sf = 5226, CODE_FOR_vec_initv8di = 5227, CODE_FOR_vec_initv8df = 5228, CODE_FOR_avx2_extracti128 = 5229, CODE_FOR_avx2_inserti128 = 5230, CODE_FOR_vcvtps2ph = 5231, CODE_FOR_avx2_gathersiv2di = 5232, CODE_FOR_avx2_gathersiv2df = 5233, CODE_FOR_avx2_gathersiv4di = 5234, CODE_FOR_avx2_gathersiv4df = 5235, CODE_FOR_avx2_gathersiv4si = 5236, CODE_FOR_avx2_gathersiv4sf = 5237, CODE_FOR_avx2_gathersiv8si = 5238, CODE_FOR_avx2_gathersiv8sf = 5239, CODE_FOR_avx2_gatherdiv2di = 5240, CODE_FOR_avx2_gatherdiv2df = 5241, CODE_FOR_avx2_gatherdiv4di = 5242, CODE_FOR_avx2_gatherdiv4df = 5243, CODE_FOR_avx2_gatherdiv4si = 5244, CODE_FOR_avx2_gatherdiv4sf = 5245, CODE_FOR_avx2_gatherdiv8si = 5246, CODE_FOR_avx2_gatherdiv8sf = 5247, CODE_FOR_avx512f_gathersiv16si = 5248, CODE_FOR_avx512f_gathersiv16sf = 5249, CODE_FOR_avx512f_gathersiv8di = 5250, CODE_FOR_avx512f_gathersiv8df = 5251, CODE_FOR_avx512f_gatherdiv16si = 5252, CODE_FOR_avx512f_gatherdiv16sf = 5253, CODE_FOR_avx512f_gatherdiv8di = 5254, CODE_FOR_avx512f_gatherdiv8df = 5255, CODE_FOR_avx512f_scattersiv16si = 5256, CODE_FOR_avx512f_scattersiv16sf = 5257, CODE_FOR_avx512f_scattersiv8di = 5258, CODE_FOR_avx512f_scattersiv8df = 5259, CODE_FOR_avx512f_scatterdiv16si = 5260, CODE_FOR_avx512f_scatterdiv16sf = 5261, CODE_FOR_avx512f_scatterdiv8di = 5262, CODE_FOR_avx512f_scatterdiv8df = 5263, CODE_FOR_avx512f_expandv16si_maskz = 5264, CODE_FOR_avx512f_expandv16sf_maskz = 5265, CODE_FOR_avx512f_expandv8di_maskz = 5266, CODE_FOR_avx512f_expandv8df_maskz = 5267, CODE_FOR_sse2_lfence = 5268, CODE_FOR_sse_sfence = 5269, CODE_FOR_sse2_mfence = 5270, CODE_FOR_mem_thread_fence = 5271, CODE_FOR_atomic_loadqi = 5272, CODE_FOR_atomic_loadhi = 5273, CODE_FOR_atomic_loadsi = 5274, CODE_FOR_atomic_loaddi = 5275, CODE_FOR_atomic_storeqi = 5277, CODE_FOR_atomic_storehi = 5278, CODE_FOR_atomic_storesi = 5279, CODE_FOR_atomic_storedi = 5280, CODE_FOR_atomic_compare_and_swapqi = 5282, CODE_FOR_atomic_compare_and_swaphi = 5283, CODE_FOR_atomic_compare_and_swapsi = 5284, CODE_FOR_atomic_compare_and_swapdi = 5285, CODE_FOR_atomic_compare_and_swapti = 5286, LAST_INSN_CODE }; #endif /* GCC_INSN_CODES_H */